Part Number: AFE7444 Other Parts Discussed in Thread: AFE7686 , Hello,
we are trying to run the boundary scan test on our AFE7444 (using AFE7686 bsdl model).
The device JTAG port is chain connected with other IEE1149 compliant devices.
When the AFE7444…
Hi Wanrui,
I believe the registers that you are looking for are registers 0x27 and 0x28 of page PLLDIG_P0, see page 186 of the Register Set document. These registers control which blocks are put to sleep when SLEEP goes high.
Regards,
David Chaparro …
Hi Wanrui,
The TI IP has been created such that you can easily take our ready made reference designs and modify them for your custom configuration. Additionally it is provided royalty free for use with TI high-speed data converters.
In regards to your…
Part Number: AFE7444 Other Parts Discussed in Thread: AFE7900 , AFE7950 Hi,
I need to setup AFE7444 mode for JESD204B protocol.
I have to employ 2 receivers and 2 transmitters (2 ADCs and 2 DACs), so totally 4 channels. Baseband I&Q samples are received…
Hi Wanrui,
In the AFE7444 you can define if certain GPIO pins are inputs or outputs. This is done by setting the direction of the GPIO pin in the register settings. If a pin should be an input and is expected to receive a signal it should be set as an…
Hi Jong-min,
Please send a hi-res picture of the AFE7444, that is the only way to back track on when the device you have was manufactured.
Regards,
Rob
Part Number: AFE7444 i use a custom board is used AFE7444 chip.
and i have a datasheet about AFE7444.
but i can not download file and join site about AFE7444 Programmer's Guide 8.3.2 Start-up Sequence(181page from datasheet).
can i get a file about…
Part Number: AFE7444 Hi ,
We have a Custom board with AFE7444 installed.
We are running it in MODE 6. Sometimes after some time like an hour, it stops transmitting the signal.
we check the temperature with 0x3c register its max going to 57 degree C. …
Part Number: AFE7444 HI ,
I am in the process of implementing the JESDIP on the Custom board with 10 Gbps rate.
I noticed in the TI JESDIP there is requirement of two clocks.
1. MGT clock .
2. SYS clock
We don't have two clock from same source in our…
Part Number: AFE7444 Hi ,
We are testing the AFE7444 with Ultrascale FPGA.
We noticed every time we change the Waveform we need to reset the DAC.
Can you know to tell us how can we fix it. or the reason behind it?
With regards,
Ganesh Singh