Hi Vijayendra,
I am coming back to you because we didn't find the good programming sequence.
Did you have a idea of the good one ?
Sincerely,
François Duclos
Hi Oleksii,
The internal test tone phases are not synchronized. Only the main signal path from JESD204 interface to DAC output delays and phases are synchronized based on SYSREF.
Regards,
Vijay
Part Number: AFE7700 Hi!
In the secure folder, AFE77XX-HSC-DESIGN file "Latte_Upgrade_Instructions.doc" contains outdated links for Lib 2.2 pathing.
Could you please fix it?
Thanks,
Oleksii Shako
Part Number: AFE7700 Hello!
In 9.3.3.3 paragraph of slose45a-rtp-final.pdf mentioned delay blocks.
Could you please provide information on configuring it separately for all TX and RX channels?
Thanks!
Hi Oleksii,
I see this issue is resolved in below post:
https://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1187712/afe7700-jesd-loopback-mode-enabling
I'm closing this post. If you have any further questions, you can open a…
Hi, Vijay!
Thanks for your answers, it helps us so much and clarified the situation.
Vijayendra Varma Siddamsetty said: I assume you mean 1 LVDS sync each for both directions.
Yes, sure. Each direction has its own sync signal.
Fortunately, I`ve got data…
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