Part Number: AFE7799 Tool/software: Hi Expert,
The JESD receiver should generate synchronization request by asserting SYNC~ signal.
In our RU system, we don't see the AFE7799 assert SYNC~ signal when initialization, and our FPGA asserts SYNC~ when initialization…
John Show said: Does the "Fb" in your reply mean "feedback path"? If so, what is the impact of feedback path to Rx path?
Fb is direct sampling and should give us an idea about the spur, however, based on the recent plot it looks within…
Hi Serkan
We have tried this API function, but got less improvement on the DC spur.
Do you have any other suggestion, or hint for debugging this?
We saw the DC offset can be reduced to at most -88dBFS in the data sheet, how can we achieve that?
Thanks…
Part Number: AFE7799 Hi expert,
Below is the ACLR test on Tx3 and Tx4 channel from customer. They used FPGA for DPD. The HW circuit design on each channel are the same, but ACLR result is different.
The yellow waveform in the figure is connected on Tx3…
Allan Fan said: setPllLoFbNcoFreezeQec(fd, 4800, 245.76, 0, 4800);
For this function, their SW team needs to use ctypes.c_double for the parameters. We are assuming their team aware of this but wanted emphasize.
For example;
setPllLoFbNcoFreezeQec(fd, ctypes…
Kang,
Allan Fan said: loopback without any signal. the noise floor is about -12dBm
This is a loopback setup without input signal and AFE Tx connect directly to the SA. So we thought the Rx input power should be no problem but don't know why output noise…
Dear Kang:
Dear Allan:
Today we test Alpha_EVM_bringup.py and loopback.py at two kinds of HW platform. Alpha_EVM_bringup.py has “AttributeError: 'NoneType' object has no attribute 'Reconnect'” issue. And loopback.py happen…
Hi Kevin & Allan,
I replied our result in email to both E2E forum and here, since we had an email last time.
According to TI suggestions, I place TI APIs before our current JESD Status Check mechanism. As shown in picture, all error messages are literally…
