• CDCLVP1102: The variation of differential output peak to peak voltage

  

  wang shu

  TI Thinks Resolved

  Part Number: CDCLVP1102 Hi, The differential output peak to peak voltage in the datasheet is 0.5V to 1.35V. Looks like it is a full frequency range spec in datasheet figure 2. my application is 80MHz, the typical value shall be close to 1.2V. What is…

  • over 3 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCLVP1102: CML Levels

  

  Henry Wang3

  Resolved

  Part Number: CDCLVP1102 Other Parts Discussed in Thread: CDCL1810 , CDCL1810A , Hi Sirs, My customer is looking for a 1:2 fanout buffer device for CML levels, may I know there have any devices can meet this request?

  • Resolved

  • over 4 years ago
  • Clock & timing
  • Clock & timing forum

• RE: CDCLVP1102: How to use CDCLVP1102 for LVDS input

  

  Shawn Han

  Only one 100 Ohm termination for LVDS connection is needed, near receiver side (CDCLVP1102 input pins). Figure 6 is DC coupling LVDS mode, Figure 7 is AC coupling Differential signal mode (including LVDS). Figure 6 uses a parallel 100 Ohm. Figure 7…

  • over 7 years ago
  • Clock & timing
  • Clock & timing forum

• CDCLVP1102: Confirm if PECL/LVPECL are still recommended for new design

  

  Jonathan Geronga

  Part Number: CDCLVP1102 Hi Team, Our customer would like to confirm if PECL/LVPECL is still recommended by TI for a new design as they find that there is a declining state on PECL/LVPECL from other suppliers. They are just looking for clarifications for…

  • over 5 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCLVP1102: LVPECL to LVDS

  

  Vincent Chen64988

  Resolved

  Part Number: CDCLVP1102 Hi Team, My customer would like to use CDCLVP1102 and the interface of receiver side is LVDS. we referred to app. note of SCAA059C for LVPECL to LVDS connection(Figure 5) and found two question. Please could team comment it.…

  • Resolved

  • over 6 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCLVP1102: CDCLVP1102 does not have the output signal

  

  Mickey Zhang

  Resolved

  Part Number: CDCLVP1102 Other Parts Discussed in Thread: CDCLVP2102 , CDCLVP1204 , CDCVF2505 Hi team, The customer is using CDCLVP1102. He uses the single-ended input. He tests the Vac_ref pin and it has a 2V voltage. The schematic is in the attachment…

  • Resolved

  • over 8 years ago
  • Clock & timing
  • Clock & timing forum

• CDCLVP1102: LVDS buffer

  

  Uday Kumar

  Part Number: CDCLVP1102 Other Parts Discussed in Thread: CDCLVD1204 , CDCLVD2102 , SN65LVDS105 Looking for a LVDS buffer – requirement is 3.3V, 1:2 LVCMOS (single ended) to LVDS differential buffer, low jitter

  • over 6 years ago
  • Clock & timing
  • Clock & timing forum

• CDCLVP1102: Relax product for input edge rate

  

  Ryuuichi machida

  TI Thinks Resolved

  Part Number: CDCLVP1102 Hello, I would like you to confirm any clock buffer which relax input transition time. According to datasheet of CDCLVP1102, min input edge rate is min 1.5V/ns. Then, I would like you to confirm solution of one of below.…

  • over 6 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCLVP1102: CDCLVP1102 for PCIe clock buffer

  

  Arthur Huang

  Resolved

  Part Number: CDCLVP1102 Other Parts Discussed in Thread: LMK00334 Hi team, customer is query if the CDCLVP1102 is suitable to use in the 1:2 PCIe clock buffer application? Please advise. Thanks. Regards, Arthur

  • Resolved

  • over 9 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCLVP1102: Data sheet interpretation:

  

  Anthony Monti

  Resolved

  Part Number: CDCLVP1102 I'm using 3.3v VCC. Section 6.8 of the cdclvp1102 data sheet list the Voh max as Vcc -.9 = 2.4V. The Vol min is Vcc-1.7 = 1.6v. I would think the max Vout Diff p-p would be 2.4-1.6 = 0.8V. The data sheet list the Max Vout Diff…

  • Resolved

  • over 7 years ago
  • Clock & timing
  • Clock & timing forum

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