Answered

• CDCLVP1204: IN_SEL Switchover Time to Stabilize

  

  Don Schelle

  Resolved

  Part Number: CDCLVP1204 Hello, We're observing some odd behaviour with the CDCLVP1204 during input switch over. Our system is as follows: Both inputs are 156.25MHz Both inputs are AC coupled (with 100nF caps) LVPECL signals and terminated…

  • Resolved

  • over 4 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCLVP1204: single-ended output

  

  Connie Lu1

  Resolved

  Part Number: CDCLVP1204 Hi team, My customer is planning to use a 200MHz LVPECL clock. For the configuration below, they want to drive the CDCLVP1204 single-ended with a square-wave. What is the recommended minimum voltage? I see recommended specs…

  • Resolved

  • over 4 years ago
  • Clock & timing
  • Clock & timing forum

• CDCLVP1204: how to count the slew rate of the CDCLVP1204, whether it's the same as the lvCMOS, 20%-80%?

  

  Frank Xiao

  TI Thinks Resolved

  Part Number: CDCLVP1204 Hi team, We want to check how to count the slew rate of the CDCLVP1204, whether it's the same as the lvCMOS, 20%-80%? Thanks.

  • over 5 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCLVP1204: difference in output voltage for Out3p vs. Out3n

  

  Ue

  Resolved

  Part Number: CDCLVP1204 Other Parts Discussed in Thread: CDCLVD1204 Hi all My customer has a design with the CDCLVP1204 and they find this problem with the output levels. Please refer to below schematic illustrating their clock distribution system…

  • Resolved

  • over 4 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCLVP1204: Random additive jiiter data for fout = 25MHz

  

  JH Shin

  Resolved

  Part Number: CDCLVP1204 Other Parts Discussed in Thread: , LMK00304 Hello, Could you please provide the random additive jiiter data for fout = 25MHz ? The CDCLVP1204 data sheet contains only the random additive jitter data for fout=100MHz or higher…

  • Resolved

  • over 5 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCLVP1204: Not monotony Vcc ramp

  

  Kazuhiko Hirano

  Resolved

  Part Number: CDCLVP1204 Hello, My customer is using CDCLVP1204 on their production board. However, recently, they realized that CDCLVP1204 Vcc does not ramp monotony somehow on their board as follows. Could this be an issue? Best regards…

  • Resolved

  • over 5 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• LMX2594: How to DC couple LMX2594 output RFOUTB to CDCLVP1204 LVPECL input?

  

  Trevor Fox

  Resolved

  Part Number: LMX2594 Other Parts Discussed in Thread: CDCLVP1204 Hi, I have an application where I need to split the LMX2594 output to two devices. I am planning on using the Ti part CDCLVP1204 (LVPECL output splitter) to split this output, and the…

  • Resolved

  • over 4 years ago
  • Clock & timing
  • Clock & timing forum

• CDCLVP1204: unused Vac_ref pin

  

  Lilian Chang

  TI Thinks Resolved

  Part Number: CDCLVP1204 Hi Team, If input signal is DC coupled VCC 3V3, LVDS input. How to connect the unused Vac_ref pin? Just leave it floating? Thank you.

  • over 6 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCLVP1204: CDCLVP1204 suitability for non-clock data fanout

  

  Nicolas V

  Resolved

  Part Number: CDCLVP1204 Support Path: /Product/Help with Device Selection/Clock or timing solutions/Overview on clock and timing solutions/ Hello, As stated in the title, I want to know if CDCLVP1204 is suitable for NON-clock data fanout buffer. Thank…

  • Resolved

  • over 8 years ago
  • Clock & timing
  • Clock & timing forum

• CDCLVP1204: What's the input clk duty cycle limitation? Whether the 20%-80% input clk duty cycle has risks?

  

  Frank Xiao

  TI Thinks Resolved

  Part Number: CDCLVP1204 Hi team, What's the input clk duty cycle limitation? Whether the 20%-80% input clk duty cycle has risks? Thanks.

  • over 4 years ago
  • Clock & timing
  • Clock & timing forum

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