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Other Parts Discussed in Thread: CDCP1803 , CDCE62005
Hello,
Can somebody explane to me why on the DAC34H84EVM the FIFO-OSTR clock has an external divider(U6 CDCP1803).
The divider is set to divided by 2. Why is this better than setting the clock…
Hi Pedro,
You're definitely better off using a dedicated clocking solution to clock your FPGA, ADC, and DAC. The "right" part will depend on how many outputs you need, the frequency range and required dividers and the type of outputs needed. The CDCM61001…
Manuel,
First off, you're looking at the wrong connector. You need to look at the FMC_DAC_ADAPTER, not the ADC adapter. This may be the source of your confusion.
http://www.ti.com/tool/fmc-dac-adapter
Note that the DAC gets its clock from the CDCP1803…
Hi Prashant,
Also note that the clock input stage has AC coupling in the DAC3152 EVM as a standard configuration. The LVPECL clock is provided with AC Coupling to DAC Clock pins DCLKP and DCLKN from CDCP1803.
If you are running the DAC at very low speeds…
Matt,
I'm still looking for other ideas to get this DAC EVM board to work. What other suggestions can TI provide? Is there a way I can verify if this board is fried? All I know is that I've never seen white smoke, smelled any burning components, etc…
Hi Greg,
You are correct that the VCO range of the CDCE62005 is out of range if Fout is set to 3.84MHz.
With the highest output divider O = 80 and Prescaler of 5, the VCO will need to be set at 3.84*80*5 = 1536MHz, which is out of the VCO range of 1.75GHz…
