Hi Alessandro,
The A|B naming is referring to the two DAC's that are in the device. FIFOA -->DACA & FIFOB -->DACB.
When i try the same config file that i gave you previously my result is no alarms for dataclk. I see that your reg zero is…
Dear Miguel Lomeli
I will remind you that this is not a problem with DAC3171 but a problem with another company's product.
If there is no similar problem with DAC3171, I would like to use it instead
The test environment is as follows
Part Number: DAC3171
Dear Technical Support Team,
Do you have any companion amp or trans for ±5V output with DAC3171?
If you have reference design , it is useful for me.
DAC3171 is current output, so I/V transfer and amp for differential to single…
Part Number: DAC3171 Other Parts Discussed in Thread: ADS4229 , LP5910 Dear Sir, We have an application where we are using the DAC3171 14-bit D/A convertor. We have it working on our board, clocked with a 500 Mhz clock, steered by a Xilinx arxiv FPGA,…
Hi Neeraj,
Here are some waveform drawings illustrating how my FPGA design is driving the DAC3171. One includes the constrained timing of the signals, and one includes the relationship between DATACLK, SYNC, and DATA[13:0].
Does anything appear off…
Part Number: DAC3171 Other Parts Discussed in Thread: DAC3174 I am struggling to get any passing results from the built-in iotest feature of the DAC3171. Additionally, there is some odd behavior in config5 register (addr 0x05) that I cannot reconcile…
Part Number: DAC3171 Hi，
I’m using DAC3171 in 7-bit mode，but finding that the lower 7 bits seems not showed because the noise floor is much higher. I think DAC3171 does not work in the 7-bit mode properly.
and I have found that the Bit 6 of config5…
Part Number: DAC3171 Other Parts Discussed in Thread: CDCE62005
I'm using DAC3171 7-bit DDR mode, but it seems like does not work in that mode.
My setting is
reg 0----0x46fc
reg 1---0x600e
reg 2---0x3f80
reg 3---0x0001
Is it right?
