hi, Richard:
thank you very much for your reply.
I tried config3 as you suggested, but it still made any difference. I also tried to decrease the dataclk frequency to 5Mhz to look what would happen, while it was the same.
I also tried to use the config20…
Hi Jimmy,
Generally DATACLK is generated in the FPGA and sent to the DAC along with the DATA. The DATA and DATACLK will need meet setup and hold time to properly latch data in the DAC. Generally DACCLK and REF clock for the FPGA( used to drive DATACLK…