Hi SM,
You are correct, 500MHz would be the max bandwidth
There shouldn't be any issues regarding pattern supplied to the DAC at all.
The interface itself will not be vastly different than if using an active mixer part. I would suggest following…
PIN_ASSIGNMENT.xlsx
Hi Richard,
Thank you for detailed answer. I have another question regarding pinouts of the DAC and the ADAPTER. I'm mapping the pins to understand what pins to define on FCM connector of the Arria 10 evaluation board. So, I encounter…
Other Parts Discussed in Thread: DAC3174 Using DAC3174, I’ve found a disconnection between the datasheet and DAC3174EVM schematic.
Pins 51, 52, 62,63 are “NC” according to the datasheet but those pins are defined as “VDDA18” on the schematic. Should…
Other Parts Discussed in Thread: DAC3174 Hello,
My customer has a question about DAC3174.
[Q]
Bypass Capacitors of VDD (such as +IOVDD, +3.3VA, +1.8VDIG, +1.8VCLK, +1.8VDAC) of DAC3174EVM are used 0.22uF.
Do you have any meaning for this value ?
(ex) It…
Other Parts Discussed in Thread: DAC3164 , DAC3283 , DAC3171 , DAC3174 , DAC3154 Hi team,
We're interested in using the DAC3164 in our design and had a couple questions:
Most FPGAs guarantee Vod (output differential) of 250 mV. Looking at the datasheet…
Hi everybody,
I'm evaluating the DAC3174 for my next project, and I need to connect the DAC3174EVM with a Xilinx FPGA board
the product page is mentioning the following:
FMC-DAC-Adapter card to connect to a standard FMC interconnect header, a typical…