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Showing 134 results View by: Thread Post Sort by
    Answered
  • RE: Baseband clock synchronization between TSW1266EVM and TSW30SH84 EVM using TSW1400 EVM

    Meenakshi Rawat
    Meenakshi Rawat
    Resolved
    Hello Jim, The register files I shown you before for TSW1266 and TSW30SH84 EVMs are not working for my new setup with TSW1400 EVM. I am not able to see any signal at transmitter output at all when signal is sampled at 307.2MHz. Previously I used to…
    • over 10 years ago
    • Data converters
    • Data converters forum
  • RE: 8 Channels and two DACs for Xilinx ZC702 FPGA

    jim s
    jim s
    Dimitri, You will not be able to install both DAC boards at the same time as there will be a physical interface issue. See attached photo of the DAC EVM. The TSW14J10EVM will not work with this setup as many of the required traces are not routed on…
    • over 4 years ago
    • Data converters
    • Data converters forum
  • DAC34H84: DAC34H84

    Eric Cui13
    Eric Cui13
    TI Thinks Resolved
    Part Number: DAC34H84 hi, I want to use the DAC34H84 to output a sine wave.The input is a 20MHz sine wave and the output is this sine wave. How should I configure this chip's register? Thank you.
    • over 7 years ago
    • Data converters
    • Data converters forum
  • RE: DAC3482: PLL lock issue

    Kang Hsia
    Kang Hsia
    Hello Wayne, The alarm_from_pll is a analog PFD detector to detect the current drift between the up/down current of the PFD to determine PLL lock. There should be some standard textbook that talks about the implementation and the potential leakage current…
    • over 7 years ago
    • Data converters
    • Data converters forum
  • TSW30SH84EVM: TSW30SH84EVM and TSW1400EVM

    Shouyan Shi
    Shouyan Shi
    Part Number: TSW30SH84EVM Other Parts Discussed in Thread: LMK04808 , DAC34SH84 Recently we had received TSW30SH84 and its driver TSW1400 evaluation boards. We follow the instruction of data sheet and video from TI. 1) Hook up both boards together through…
    • over 8 years ago
    • Data converters
    • Data converters forum
  • RE: Possibility for connecting between DAC3484 and FPGA

    Kang Hsia
    Kang Hsia
    Hi Kyle, When we released the DAC3484, we have specified the DAC LVDS receiver input level to match Xilinx FPGA (Virtex 5/6 series at the time of the release) to meet their LVDS output requirement (both AC swing and DC common mode spec). As long as…
    • over 10 years ago
    • Data converters
    • Data converters forum
  • RE: DAC3482: abnormal floor noise and spur after power up

    Kang Hsia
    Kang Hsia
    Hello Jerry, The config 0x24 (or config36 register) is to tune the setup/hold time of the LVDS bus. The setup/hold time can be adjusted through internal LVDS data or dataclk delays to match the external timing. The minimum setup/hold time needed for…
    • over 6 years ago
    • Data converters
    • Data converters forum
  • Answered
  • RE: ADC32J44: How to wire up unused SYNC pins

    jim s
    jim s
    Resolved
    3201.JESD204B Overview April_2016.pptx Variac, This is a JESD204B based device and you have to use SYNC to get the link established. There is no way around this. See the attached document for an overview of this standard. Regards, Jim
    • over 7 years ago
    • Data converters
    • Data converters forum
  • RE: DAC34H84

    jim s
    jim s
    new2day, This document should help with your issue. Regards, Jim DAC Synchronization.pdf
    • over 8 years ago
    • Data converters
    • Data converters forum
  • RE: testing DAC3484

    jim s
    jim s
    Ramakrishna, Since you are using four DAC's, the DACCLK will have to be 4X the data clock, not 2x like I mentioned in the earlier post. You could pulse the OSTR once but you must also make sure the Frame signal only pulses once as well. One resets the…
    • over 9 years ago
    • Data converters
    • Data converters forum
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