Part Number: DAC38J82 Other Parts Discussed in Thread: TEST Hi team,
Here is a question from one of our customers:
When using DAC38J82EVM , I use DDS on FPGA to generate a sine wave and output it. The waveform measured by oscilloscope is as follows:
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Amy,
1. No. Either the DAC input clock or the DAC PLL VCO is used by the Serdes PLL. The FIFO errors and others will not be valid until the Serdes PLL is locked and they are cleared by writing "0" to them.
2. No. No.
3. Makes sure the customer…
Part Number: DAC38J82 Hello All,
I'm working with DAC38J82 in a customised hardware. I'm having an issue in getting the DAC output. Here is my configuration.
DAC input clock is 2457.6MHz. DAC PLL is not used. No SYSREF input.
I'm trying to use…
Part Number: DAC37J82 Other Parts Discussed in Thread: DAC38J82 Table 47 on Page 69 of the datasheet shows the following register configuration for register 16:
The datasheet says:
The QMC correction phase term for the DACAB path. The range is –0.5 to…
Part Number: DAC38J82 Other Parts Discussed in Thread: DAC38J84 , TSW38J84EVM , DAC38RF82
Hi all, I'm trying to bring up the DAC38J82 to operate with complex samples. I need few clarification regarding the internal path flow. I understand that the DAC38J82…
Part Number: DAC38J82 Dear sirs,
Could anybody tell me how can I control the output gain of the DAC ( DAC GAIN ) . I have used the Mixer_gain: 6dB and the Qmc_gainA and Qmc_gainB with another 6dB , but I cant find the DAC GAIN as shown on the Functional…
Part Number: DAC38J82 Other Parts Discussed in Thread: TEST , Hello, I am using a LMK 04828 along with a DAC38J82. An FPGA is transmitting ADC samples to the DAC and the LMK is providing all clocks. A few things about my board: Dclkout0_1 is for the Dac…
