Other Parts Discussed in Thread: DAC38J84 , LMK04828 , DAC37J82 , DAC37J84 , DAC38J82 , DAC39J82 , DAC39J84 Hello,
I have a DAC37J84EVM in a system. Since I know the required register values, is there a way I can "hard-code" it so that it comes up configured…
Part Number: TSW14J57EVM Other Parts Discussed in Thread: DAC38J82 , , LMK04828 Hi everyone,
I'm using a TSW14J57 eval board connected to a DAC38J82 eval board. I intend to use the trigger mode, so that I can both generate a desired waveform from the…
Yuval,
See attached regarding question #1.
For question #2, the data sheet looks this way because it is using de-embedding, which attempts to remove the parasitics from the measurement – like balun, pcb traces, connectors etc.
Regards,
Jim
JESD…
DAC38J82_421_983p04.pptx 7181.DAC3xJ8x Device Initialization and SYSREF Configuration.pdf 156.25_LMF_4211.cfg Kyle,
We are very short handed right now due to trade shows and vacation. See if the following helps. I am assuming you are interpolating by…
Other Parts Discussed in Thread: DAC37J82 , DAC38J84 I am using the DAC37J82 with LMFS = 2221. I am using lanes 3 and 2 (setting 0x4A to 0x0C21), with continuous SYSREF and skipping 2 sysrefs then using all (0x5C to 0x0006). However, when I generate JESD…
I've tried with DAC PLL enable as in A10 DAC38RF82 7p68G 84111 Reference Design User Guide.pdf .
There are still no outputs and more error messages :
Now two more errors about write and read error besides FIFO empty.
Question : would A10 firmware…
Todd,
you may refer to attached information for CDR setting. By default, we have tested CDR setting of 000 for JESD204B. You can tweak your CDR setting and use along with PRBS testing highlighted in 7.3.19 to gauge statically your link quality. Unfortunately…
Hello,
The first configtbd is the alarm registers located from config100 (0x65) to config109 (0x6E)
The second configtbd is located in config3 with respect to the DAC output gain
the third configtbd is located in config27 for external reference…
Todd,
Section 7.3.2 and section 7.3.3 are strictly highlighting the SERDES PLL, which is different than the DAC PLL (7.4.12).
The SERDES PLL will basically take a reference clock (a divided down clock from the DAC PLL or directly from external clock…
