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  • DAC38J84EVM: DC Coupled Sysref

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    Part Number: DAC38J84EVM Other Parts Discussed in Thread: DAC38J84 , LMK04828 Hi I am using DAC38J84 EVM. In the Datasheet, it is mentioned that Clock and Sysref Standard is LVPECL (AC Coupled). But in the EVM Schematics, Sysref is DC Coupled . So rec…
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  • DAC38J84EVM: EVM no response

    Resolved
    Part Number: DAC38J84EVM Other Parts Discussed in Thread: DAC38J84 I'm designing my third-party FPGA( XILINX KCU040 kintex ultrascale ) evaluation board with a standard FMC-HPC connector to DAC38J84EVM. All jumpers at DAC38J84EVM are left untouched…
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  • DAC38J84EVM: DAC PLL out of lock

    Resolved
    Part Number: DAC38J84EVM Other Parts Discussed in Thread: TI-JESD204-IP , LMK04828 Dear Ti. I'm using xilinx FPGA kcu040 kintex ultrascale trying to drive the DAC38J84EVM, all pins should have been assigned properly. I have tried both TI-JESD204-IP…
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  • DAC38J84EVM: Why the data lines are jumbled up?

    Resolved
    Part Number: DAC38J84EVM Other Parts Discussed in Thread: DAC38J84 Hello, The data lines from FMC to the DAC are jumbled up. For example, DP5_C2M from FMC is connected to RX7. It is true for other data lines also. Why is it connected this way? Please forgive…
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  • DAC38J84EVM: SYNC signal of JESD204B PIN at FMC is not connected

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    Part Number: DAC38J84EVM Other Parts Discussed in Thread: DAC38J84 DEAR TI, I am using a third party alinx xczu9eg ultrascale+mpsoc development board for JESD204B based DA development(DAC38J84EVM), The FMC daughter board I am using is DAC38J84EVM , where…
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  • DAC38J84EVM: Questions for DAC design with a 3rd party evaluation FPGA board

    Resolved
    Part Number: DAC38J84EVM I'm designing my third-party FPGA( XILINX Zynq UltraScale+ XCZU9EG MPSoC ) evaluation board with a standard FMC-HPC connector,which is not in the support list of HSDC pro software. My question is following: 1.weather and…
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  • DAC38J84EVM: How to enable DAC output with fixed delay

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    Part Number: DAC38J84EVM Other Parts Discussed in Thread: LMK04828 , DAC38J84 Hi, I am use a sys_sync signal to enable the DAC output. After the rising edge of sys_sync signal reach to the SYNC of LMK04828, there are outputs on the SDCLKout*. I can capture…
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  • DAC38J84EVM: SYSREF to NCO phase reset delay inconsistency

    Resolved
    Part Number: DAC38J84EVM Other Parts Discussed in Thread: DAC38J84 Hi, I am using the DAC38J84 on the EVM with an Arria10 dev board and for now, the JESD part works fine. However I am facing a problem using the NCO on this DAC. For my project, I plan to…
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  • DAC38J84EVM: How to get the full scale output?

    Part Number: DAC38J84EVM I enable the NOC function, set the Coarse DAC Gain to 10, the mixer gain disabled, I get 0.95V Vp-p, is it right? How can I get 1.5V Vp-p? Thanks!
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  • DAC38J84EVM: Respecting the hold and setup times of the SYSREF with DACCLK at 2.457GHz

    Resolved
    Part Number: DAC38J84EVM In pll disable mode, the DACCLK is used straight from the pin and SYSREF needs to respect the setup and hold times. On the eval board, the LMK can generate up to 2.457GHz for the device clock with the divider set to 0. However…
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