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  • RE: DAC38RF82: Link configuration error for one lane

    Hi Oddbjørn, Here is the feedback from design: There is not any internal source of offset that could explain the results. It is interesting that the amplitude of the tone is -53dB relative to fullscale – which is ~ 1/512, so maybe something with…

  • DAC38RF82: 81180 9G mode cannot output

    TI Thinks Resolved
    Part Number: DAC38RF82 Hello, Our customer used DAC38RF82 for his application, when configuring DAC38RF82 81180 mode, 8G sample rate can be output, but 9G cannot output. DAC38RF82 81180 9G mode does not output. Using internal PLL, input clock 281.25MHz…
    • Answered

  • DAC38RF82: Configuration Setup Question

    Resolved
    Part Number: DAC38RF82 Hello, I would like to confirm a proper configuration for DAC38RF82 for our application. We need to create a baseband signal (coming from FPGA) of bandwidth between 50-100MHz (Internal data rate will be 100-200MSPS). This is a single…
    • Resolved

  • RE: DAC38RF82: DAC38RF82 JESD204B Frame format for for LMFSHd = 41380

    Hi Mingming, We do not have a tool for generating these. To make these tables I took the data sheet JESD frame format and used that to make the 32 bit data width that the FPGA uses. The LMFS that you mention all have a F of 3, meaning that they have…

  • RE: DAC38RF82: output issue

    Hi Cherry, Additionally, can you explain the format of the initial registers provided? Is this 8 bit address and 16 bit data? I cannot get the link up using the customer's configuration. Please provide the customer with both of these files below to try…
    • Answered

  • DAC38RF82: SERDES and lane configuration

    Resolved
    Part Number: DAC38RF82 Hi, Expert : I have one question about DAC38RF82. We swap lane connection between FPGA and DAC because of layout. The SERDES lane connection diagram is illustrated as the below and need help to confirm the SERDES and lane configuration…
    • Resolved
    • Answered

  • RE: DAC38RF82: DAC38RF82

    Resolved
    If using LMF = 421, you can only have one NCO for DAC_A. If you are setting the VCO to 8.9GHz, the register values for a 1.2GHz NCO is as follows: Page 1 Add 0x1E Data 0x1142 Add 0x1F Data 0x508A Add 0x20 Data 0x2284 Not sure why you are talking about…

  • RE: DAC38RF82: Some DAC AB channels have only NCO frequency output

    Hi Jim, jim s said: Can they send a schematic showing how SYSREF is connected between the DAC and SYSREF source? The RFoutB of the LMX2595 yields a SYSREF of 1.5625 MHz, which is given to the LMK00304 and outputs four SYSREF of the same source to four…
    • Answered

  • DAC38RF82: Can DAC38RF82 Operate without SYSREF?

    Resolved
    Part Number: DAC38RF82 Hi expert, If customer don’t have multiple chips to synchronize or deterministic latency demand, could they ignore SYSREF+/- e.g. floating or tie to GND? In addition, we see register 0x24 & 0x5C SYSREF_MODE can be set "Don…
    • Resolved
    • Answered

  • DAC38RF82: DAC JESD FIFO offset

    Resolved
    Part Number: DAC38RF82 Hi, Expert : I need help to suggest a suitable setting of DAC38RF82 JESD FIFO offset (page 0/1, register 0x0D Bits[10:8]). The power-on default value is 000b and this is a good choice or not? Please advise & thanks. Yao-…
    • Resolved

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