Part Number: DAC38RF82 Hello,There
We are now debugging DAC38RF82, In the mode LMFSHD=42111 ,meet the problem of elastic buffer match error.The first non-/k/ doesn't match "match_ctrl" and "match_data" programmed values.
When issue occurs, is only the FPGA JESD IP reset or are they resetting the DAC as well? Are the clocks interrupted during this reset?
Can the customer try using an external 6.4GHz clock to see if the issue is possibly related to the DAC PLL?
Part Number: DAC38RF82 Hello Guys,
Our customer have the following inquiries:
"In DAC38RF82 datasheet, the output power level vs frequency is given as Graphical plot (attached), In that , as the frequency increases power level decreases. But…
Part Number: DAC38RF82 Hi team,
I'd like to design 2.3GHz-2.5GHz, typical 0.5dBm output system with two lanes input to the DAC.
Should DAC38RF82 support the above application?
If so, could you please let me know the recommended input configuration…
Part Number: DAC38RF82 Hi,
We are able to access the DAC registers.
The DAC is Configured following 81180 Mode.
Line Rate is 6.25 Gbps, DAC Sampling Clock generated 5 GSPS.
F=1 & K=32, so Sysref Generated : 19.53125 MHz. DAC Device clock for FPGA : 156…