Part Number: DAC38RF84 Hi Experts,
Good day. I have this query from client:
It shows that two NCO of DAC38RF84 can switch to change one frequency to another frequency quickly. Page #35 of DAC38RF84 D/S, it showed the outputs of NCO1 and NCO2 were summed…
Part Number: DAC38RF84 Hi, there :
Bit 0 of "Divided Output Clock Configuration Register" in DIG_MISC page is EXTREF_ENA.
The description says it allows the chip to use external reference or internal reference.
Does it mean CLK_OUT use either…
Part Number: DAC38RF84 Other Parts Discussed in Thread: DAC38RF80 , AFE7950
Dear sir,
We try to use DAC38RF84 to generate a frequency hopping tones through internal NCO of DAC38RF84.
1. Because we don't require baseband modulation, can the DAC38RF84…
Part Number: DAC38RF84 Other Parts Discussed in Thread: DAC5681
Hello, Can you provide a spur calculator spreadsheet for the DAC38RF84? I found a posting for a calculator for the DAC5681 (below), but it is missing a lot of features of the RF sampling…
Part Number: DAC38RF84 Hi Team,
Could you please check the below customer error codes to make sure i'm 100% correct. Customer is evaluating DAC38RF84, and is testing using LMFSHd = 82121, interpolation 6x, 8x. From table 44 of the datasheet this configuration…
Part Number: DAC38RF84 Other Parts Discussed in Thread: DAC38J84 Hello,
I am developing an FPGA design that has to drive the DAC38RF84 through the JESD204B I/F.
It would be useful a Verilog/System Verilog model for RTL simulation during the development…
Part Number: DAC38RF84 Other Parts Discussed in Thread: DAC38RF85 Hi,
Can you please confirm me that if we want to use the DAC28RF84, we can not use the order values of interpolation of 6 and 8? (table 9, page 44, SLASEA3C datasheet)
In this case what…
Part Number: DAC38RF84 Hi,
would it be possible to get more information regarding the manufacturing processes use to make the part? is it made only of silicon?
Regards
Other Parts Discussed in Thread: DAC38RF84 , TI-JESD204-IP Hi,
In my design i plan to interface the DAC38RF84 with Kintex 7 FPGA, my Tx IP transmits two buses (I and Q each 16 bit wide), so 2x16.
Questions:
1. will the TI-JESD204-IP be able to support this…