Part Number: DAC38RF89 I need to get the Eye Scan GUI software for testing a DAC38RF89, the SLAA762 says how to run the test but says we have to request the software on E2E. I found a link under this post https://e2e.ti.com/support/data-converters-group…
Part Number: DAC38RF89 Other Parts Discussed in Thread: DAC38RF93 Hello,
I ran into a problem recently with trying to run HSDC Pro to troubleshoot a suspected JESD problem with our DAC38RF89 implementation. I installed from the website, but get a "Missing…
Part Number: DAC38RF89 Hello,
We are using the DAC38RF89 and we encountered a problem at -20 deg temperature.
The output transmits 200M to 4G at full scale power.
The power delta at 25 deg is about 6dB for this frequency bandwidth, between the power…
Part Number: DAC38RF89 Hi Team,
The customer use a self-study board to develop LMFs=8212 for DAC38RF89 with the following configuration:
The JESD204B design on the FPGA side is as follows:
When DDS-IP on the FPGA side is enabled to send to the…
Part Number: DAC38RF89 Other Parts Discussed in Thread: DAC39J84 , , We would like to characterize the signal integrity of the gigabit transceiver lanes.
I found this thread which describes the use of the IEEE 1500 interace through JTAG for the DAC39J84…
Part Number: DAC38RF89 Other Parts Discussed in Thread: LMK04828 The DAC output is 1100MHz. There are spurious of 1M and 37.5M, respectively.
The PLL configuration of the DAC is as follows：0x31 0x0400； 0x32 0x0508；0x33 0x2A24.
The DAC clock is 200MHz of…
Part Number: DAC38RF89
Hello,
Some questions regarding the DAC38RF89 Currents:
1. In Figure 149 (Power Supply Scheme) The VDDDIG1 Current shown is 2.5A ;
While in the "Electrical Characteristics - DC Specifications" (Section 7.5) The Max Current…
Part Number: DAC38RF89
Hello,
I'm Using the DAC38RF89I and wanted to know what is the best way to place the BALUN peripherals.
For mechanical issues I can't use parts in the Print side (P.S) with thickness bigger then 0.3mm, so the inductors could…
Part Number: DAC38RF89 Hi, Our customer have two questions.
1 Is there a spec for the output jitter of the internal PLL (including VCO)? Also, is there a way to calculate jitter?
2. If we set the same data for two outputs and start sending, Will there…
Part Number: DAC38RF89 When debugging, everything works well when 204B interface channel rate is 10G. When a t 12G, the SYNC signal is occasionally pulled low, causing resynchronization.
The other registers are unchanged, except for the corresponding modification…
