Part Number: DAC38RF89 Other Parts Discussed in Thread: LMK04828 The DAC output is 1100MHz. There are spurious of 1M and 37.5M, respectively.
The PLL configuration of the DAC is as follows:0x31 0x0400; 0x32 0x0508;0x33 0x2A24.
The DAC clock is 200MHz of…
Part Number: DAC38RF89
Hello,
I'm Using the DAC38RF89I and wanted to know what is the best way to place the BALUN peripherals.
For mechanical issues I can't use parts in the Print side (P.S) with thickness bigger then 0.3mm, so the inductors could…
Part Number: DAC38RF89 Hi, Our customer have two questions.
1 Is there a spec for the output jitter of the internal PLL (including VCO)? Also, is there a way to calculate jitter?
2. If we set the same data for two outputs and start sending, Will there…
Part Number: DAC38RF89 When debugging, everything works well when 204B interface channel rate is 10G. When a t 12G, the SYNC signal is occasionally pulled low, causing resynchronization.
The other registers are unchanged, except for the corresponding modification…
Part Number: DAC38RF89
Hello,
Some questions regarding the DAC38RF89 Currents:
1. In Figure 149 (Power Supply Scheme) The VDDDIG1 Current shown is 2.5A ;
While in the "Electrical Characteristics - DC Specifications" (Section 7.5) The Max Current…
Part Number: DAC38RF89 HELLO, I use DAC38RF89 with the mode LMFSHd = 82380 1X,the FPGA is XC7K410T-2FFG900, NOW the link of jesd204b is ok, but the output of
DAC wave form is incorrect , so I doubt that the sequence of the data I arranged in FPGA endding…
Part Number: DAC38RF89 Hi,
In the section 8.3.20 of the datasheet, table 44,the outsum block perform rounding operation after addition.
Why use bits[16:1] from the result when only one channel is added? Isn't it half the result?
I think that…