Part Number: DAC39J84 Other Parts Discussed in Thread: LMK04828 Hi there,
I have multiple DAC39J84 ICs to be synchronized. Each DAC39J84 is clocked by an LMK04828.
In a related thread , ±1 VCO cycle error for LMKs' output device clock aligning was found…
Part Number: DAC39J84 Are there any pullup or pulldown requirements for the jtag interface? In the evaluation board package it does not show any aside from the TRST needing a pulldown when JTAG is not in use.
Part Number: DAC39J84 Can the DAC3XJ8X family output a test tone, independent of a functioning JESD interface? Assume it is given a reference clock, and the it 's internal PLL is programmed as needed. Can I output a tone using coarse N*Fs/8 or the…
Part Number: TSW14J57EVM Other Parts Discussed in Thread: DAC39J84EVM Hi
As part of my learning I am using DAC39J84EVM and TSW14J57EVM to establish the JESD204B data transfer from Host side to the output of the DAC. As part of it, I would also like to…
Hi Jim
Good news - it looks like we have a resolution for this. It seems that there was an issue in the HDL that meant the reset pin corresponding to RESETB was mapped somewhere else, and when I thought we were actually toggling RESETB, it was not toggling…
Part Number: DAC39J84 Hi there,
I implemented the 2x interpolation on DAC39J84, which gives me a better looking spectrum and pushes the image frequency away.
In my case, with 2x interpolation, the DAC output sample rate (f_DAC) is 2 GHz. The input…
Part Number: DAC39J84 Hi Experts,
We have this query from Cx about erroneous register map shown in SLASE48A .
Looking at D/S of DAC39J84, the addresses in Table 30 do not correspond to their matching descriptions as shown in subsequent sections. In particular…
Part Number: DAC39J84 Other Parts Discussed in Thread: LMK04828
Dear all,
I'm struggling with the configuration of the DAC39J84.
I do not see any outputs from the DAC due to errors on the lanes. Even if I'm able to perform the NCO test and the…
Part Number: TI-JESD204-IP Other Parts Discussed in Thread: DAC39J84 Hi, I downloaded TI-JESD204B IP and use zc706_8b10b ref design for VC707 fpga board and DAC39j84. I use LMFS=8411 and HD=1. Here are few questions that bug me during my implementation…
Part Number: DAC39J84
I want the DAC39J84 output converted to single ended SMA connector.
On the datasheet sec 7.3.28 and 7.3.29, it give two simple circuit for the DAC output single ended.
But on the evaluation board, it is using a 75 ohm balun (JTX…