Part Number: DAC39RF10 Tool/software: In the case of using the Fast Reconfiguration Interface in DDS mode, should the DP_EN be toggled every time the frequency is switched and sent? Please provide detailed register initialization steps regarding DDS…
Hi Hirano-san,
Please send me a picture of the DAC EVM they are using.
Also, please send me a picture of the DAC device on the EVM.
It is possible the customer is using an older pre-released EVM and/or device.
Thanks,
Rob
Part Number: DAC39RF10-SP Other Parts Discussed in Thread: DAC39RF10-SEP Tool/software: I am performing an availability analysis for a system containing a DAC39RF10ACLNSP and need (preferably) the Single Event Effect test report or (at a minimum) the…
Part Number: DAC39RF10 Hello,
I am facing one problem trying to using SPI Interface for DAC39RF10. I have developed a firmware module inside one FPGA, and when I try to load register by register (only one at a time), DAC understands it is working on…
Part Number: DAC39RF10 Hello Team,
under Material attribute search (ti.com) I find below information. My question:
Does the IC net weight include the FCBGA package or not?
Thank you and Best Regards,
Hans
Part Number: DAC39RF10 Hi everyone,
I'm working with the DAC39RF10 and have a few questions regarding its performance:
RF settling time: After the NCOs have been configured, what is the RF settling time of the DAC39RF10?
Maximum frequency in NCO…
Part Number: DAC39RF10 I would like to use this part with Versal FPGAs from AMD/Xilinx which have 1.5V max I/O bank voltages, but noticed that this part's VDDIO has a recommended range of 1.71 to 1.89V. Is it possible to operate VDDIO at 1.5V logic…
