Part Number: DAC5662 Hello,
I'm trying to build out a simple long-range mesh networking system. The data load is very low, but it is mainly to have numerous access points join my network over varying distances/environments...etc. I recently found myself…
Other Parts Discussed in Thread: DAC5662 Hi engineers
can you help me about the DAC5662 Thermal Resistance(Junction to Ambient/Board/Case)?
Thank you very much.
TIS: johnsin tao.
Hello,
There is the tsettle In the datasheet P.14 figure 19 and there is the settling time in the datasheet P.6. Is the tsettle meaning settling time? Thus, is the tsettle time 20ns(typ)? Best Regards, Ryuji Asaka
Other Parts Discussed in Thread: DAC5662 Hello,
Could you please let me know the timing requirement between SELECTIQ and WRITEIQ/CLKIQ/D[11:0]/RESETIQ for figure 19 in the DAC5662 datasheet P.14? Best Regards, Ryuji Askaa
Other Parts Discussed in Thread: DAC5662 Hello, The customer would like to control the IOUTA and IOUTB output as the attached image. I think that we can use DAC5662 on this operation by the interleave mode however, could you please check it?
Mode is…
Other Parts Discussed in Thread: DAC5662EVM Hi,
I tried to evaluate the DAC5662EVM.
For first try, I set J9 to constant data, all '0' exept one bit that is '1', entered a 40hz clock to WRT1, 50 ohm resistor to Iout1(J1).
Can someone advice on the…
Other Parts Discussed in Thread: DAC5662A Hey there,
I want to operate a DAC5662A with a clock frequency of 48MHz. The clock and the data comes from motherboard equipped with a Xilinx FPGA and the DAC will be on a analog I/O daughtercard.
I searched…
