Hi Kuo Kwan Chan,
After the data is latched into the device with rising edge of WRT signal you need 4 additional sampling clock cycle to get the data converted out of the device.
Under section 6.9 page 9 Switching characteristics table tLAT (clock…
Hi Eli,
Please recommend using the DAC5652A - it has same performance, but does not have as strict power sequence requirements. The AVDD and DVDD can come up independently. The AVDD-DVDD maximum voltage difference requirement on DAC5652 is +/-0.5V (AVDD…