Part Number: DAC5687 I have two FPGA data streams running at 250Mhz with signals covering a range of 700Khz to 90MHz. I'd like to input the two real 250Mhz signals, bypass any mixing, just interpolate by 2 and have two outputs covering the same 90MHz range…
Part Number: DAC5687 Hello, My customer has some questions about timings as follows. Q1: In datasheet figure 50, what ns is the minimum ts(TXENABLE)? Q2: Any minimum th(TXENABLE) spec? Q3: Datasheet specifies minimum ts(SDENB), but how about minimum…
Part Number: DAC5687 Other Parts Discussed in Thread: DAC8822 , Hello?
As the title, in order to reduce the number of buses, only one DATA BUS is used and inquiring about the control method of IOUTA and IOUTB.
In the datasheet, I confirmed how to output…
Hita-San,
I was able to get this setup working today using proper production material.
A few notes,
I recommend using PLL_LOCK to clock the FPGA. In this mode PLL_LOCK will output 16 MHz as the CMOS input bus has to run at twice the speed as the input…
Part Number: DAC5687 Hello, My customer gas some questions about RESETB as follows. Q1 How much is minimum LOW pulse width of RSTB to reset the DAC5687 during operation? Q2 How long should the RSETB be LOW after power up or supplying all clocks and…
Part Number: DAC5687 Hello, The datasheet page 10 specifies minimum and typical CLOCK INPUT (CLK1/CLK1C, CLK2/CLK2C) differential voltage. My customer would also like to know the maximum value. Best regards, K.Hirano
Part Number: DAC5687 Hello,
My customer has a question about The CLOCK INPUT differential voltage specified in the datasheet (0.4V/min, 1V/typ). Which is it, (CLKX-CLKXC)pp or (CLKX-CLKXC)pp/2? Best regards, K.Hirano
Part Number: DAC5687-EP Other Parts Discussed in Thread: DAC5688 Dear TI,
We are currently using DAC5687-EP on one of our Software Defined Radio Design and we encountered some trouble with the DAC5687-EP.
It seems that we have spurs with a frequency equals…
