Part Number: DAC5689 Other Parts Discussed in Thread: DAC5686 , DAC5652 Hi Guys
we have a new requirement about high speed DAC:
single CH or Dual CH output. output frequency 200MHz. Base on my FPGA system, we need parallel CMOS interface. No LVDS and JESD204B…
Part Number: DAC5689 Hello support team.
I have a question from my customer regarding how to use in dual clock mode.
Regarding how to use, CLK2 is continually input and CLKO_CLK1 is controlled inputting ON or OFF by clock source.
(CLK1C is AC coupled…
Part Number: DAC5689 Hi,
My customer observed bit shift for several ms in their system with DAC5689, so I would like to help them identify the cause. Is there any possibility that DAC5689 happens bit shift?
Regards,
Itoh
Part Number: DAC5689 I am still not seeing the output waveform I expect. If I drive a full scale triangle wave in to the channel A digital port in signed integer mode please draw the resultant waveforms out of the IOUTA1 and IOUTA2 pins.
Input waveform…
Part Number: DAC5689 I am Using a pair (4 channels) of DAC5689 converters. In the initial design I want to run them in a straight through mode with only an input clock (200MHz) and an output clock running at the same rate. .
My problem is that I cannot…
Part Number: DAC5689 Team,
I have a customer that wants to generate a waveform at 1Mhz with at least 250 points per cycle. Their intention is not necessarily a nice clean waveform, just a wavy profile to drive s mems device. They are currently considering…
Part Number: DAC5689
Dear Technical Support Team,
I have some questions about DAC5689.
1.) Is it correct understanding about t_align below?
We use fclk2=672Mhz and t_align is 190ps based on datasheet.
So rising edge relationship between CLK1 and CLK2…
Other Parts Discussed in Thread: DAC5689 Hello,
If B-channel data of DAC5689 is not used (I only need A channel data to optimise the I/Os interface between the FPGA and DAC).
Question : all unconnected pins DB(15..0) should be left open or connected to…
Other Parts Discussed in Thread: DAC5689 Hi all,
A certain user using DAC5689 is designing by rule called CLK1= 112 MHz, and CLK2= 672 MHz ('x6'). CLK1= 112 MHz (it consists of system clock so) CLK2= 672 MHz -- the maximum of 800 MHz or less …
Other Parts Discussed in Thread: DAC5689 Hi all,
DAC5689 Datasheet.
Although it is a setup of t_align on a datasheet, it is 0.19 ns as xample at the time of 672 MHz, t_align is set to NG at the time of 0ps, +40ps, and +80ps, and serves as OK at the time…