Thong,
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I mentioned last time that I found the testbench. This testbench wasn't the exact one used on the DAC8742H, but it was derived from that Labview used…
Part Number: DAC8742HEVM Other Parts Discussed in Thread: DAC8742H Tool/software: I am using two DAC8742HEVM to develop HART communication in which one serves as transmitter and the other serves as receiver. The transmitter board's MOD OUT is connected…
Part Number: DAC8742H Tool/software: I am currently using a DAC8742H as a HART modem and was wondering about the behavior of the digital reset input. I plan to use the DAC8742H in UART mode and never change the configuration inputs (XEN, CLK_CFG0, IF_SEL…
Part Number: DAC8742H Tool/software: I am currently using a DAC8742H as a HART modem with internal filtering, voltage reference, and oscillator. The datasheet for the DAC8742H explains that the internal filter uses less components than an external filter…
Ibrahim,
The setup for the transmission of the PAFF data is done through a four byte sequence as described in section 7.4.2 in the datasheet that describes the UART interfaced PAFF communication. The four bytes are shown in a diagram of the bytes and…
Part Number: DAC8742H Other Parts Discussed in Thread: PROFIBUS , Hi to all,
We are working with one customer who is interested in developing a device that could support all the three protocols the DAC8742H offers. This part fit perfectly in their requirements…
Part Number: DAC8742H Other Parts Discussed in Thread: DAC8740H , DAC161S997EVM , DAC161S997
Hi Team,
Please help to advise the power consumption of DAC8742H and DAC8740H.
In the datasheet, there is only statement for the external crystal, still need for…
Part Number: DAC8742H Hello TI
We are developing a sensor data gathering and management system, which requires a Foundation Fieldbus Interface. Our project has a 4-20mA current loop physical layer. And it is already implemented.
In this regard, we would…
Part Number: DAC8742H Hi !
We are using the DAC8742H in HART mode and have configured XEN, CLK_CFG0 and CLK_CFG1 to accept an external CMOS clock source (generated with a function generator) running at 3.6864 MHz (line 1 in Table 1 on page 16 of the data…