Part Number: DDC2256A Hi, I am not successful in writing and reading the registers of the DDC2256A. As I understood
EVERY write must be preceded by a RESET signal. This reset resets the internal state machine of the chip, but also sets the default values…
Part Number: DDC2256A Hello,
I am working with this device and am able to see data when the ADC is commanded to output the pre-defined patterns (all zeros, all ones, ramp, etc).
When I try to collect actual live data, I am not seeing the data change.…
Other Parts Discussed in Thread: DDC2256A , DDC264 Hello everyone.
I'd like to use DDC2256A (Analog-to-Digital Converter). It has 256 channels and the maximum data rate = 17 KSPS
I was wondering, 256 channels and 17 KSPS here mean that If I use all of…
Part Number: DDC2256AEVM Other Parts Discussed in Thread: DDC2256 , AFE2256 Hi TI expert
Trying to figure out which DDC2256 or AFE2256 EVM will be best for my system. Looking for a system that can read current the 15 - 90 nAmp range with a +/- resolution…
Part Number: DDC2256A In table on page 32 of the April 2016 datasheet, register 0x3A[6] indicates FCLK output will be an LVDS output when set to 1; otherwise, when set to a 0, the output will be CMOS.
On page 24 section 8.3.9, however, the datasheet states…
Part Number: DDC2256A After setting DDC2256A's ENABLE_TEMP_SENSOR (0x25[7]) to 1, datasheet indicates data header becomes 24bit + 16bits corresponding to temperature sensor + 8 zeroes. Is this true for both 24bit and 20bit data word modes? Or, when…
Part Number: DDC2256A Hi TI‘s expert,
I am a R&D manager of China Liao Ning Doctor Kaili Technology Co.Ltd. Our product need a chip DDC2256A, but we just find the chief PDF of DDC2256A. So I want to know how to get a detailed technical specifications…
Part Number: DDC2256A Hi TI‘s expert,
Currently I am designing a deserializer for DDC2256A and Xilinx Zynq-7000. The inputs for deserializer are standard: DCLK, FCLK and DATA are outputs of ADC and CONV is generated inside FPGA. The output of the…
Part Number: DDC2256A Hi all,
The DDC2256A brief data-sheet indicates 17KSPS per channel.
Q1: Does it means that if only one channel is being sampled the acquisition rate will be 17KSPS, hence for 128 channels acquisition it would be 128 times slower?
Q2…
