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Part Number: DDC316 We're gonna implement the DDC316 in combiatnion with an FGPA. Is there any VHDL which might is a good starting point?
Also is there maybe a provided VHDL enitity which can be used in simulation?
thanks
Part Number: DDC316 Other Parts Discussed in Thread: DDC264 , , DDC232 , DDC112
Hi Expert,
We need your help to suggest a device for our customer. Here is the full detail below. The customer would be interrested on this product to measure current from multielectrodes…
Part Number: DDC316 Other Parts Discussed in Thread: DDC264 Hi,
is it possible to reduce a given photodiode current at the DDC316 input in order to aviod a saturated signal?
(The integratoin time is already at 11µs and the capacitor setting is 12pC)…
Part Number: DDC316 Hi,
I wish to come back on this DDC316 topic which I have posted couple of months ago.
We follow the link you sent out and downlaod the sample circuit diagram.(Attached File) doc01837120200309162027.pdf
We are in the final stage of…
Part Number: DDC316 Hi,
When the ADC chip is set into Test Mode 3 (TM[1:0] 11), the RANGE bit settings can be changed without any problem. When a new conversion is occurred after changing the settings of RANGE bit, the output with the new RANGE settings…
Part Number: DDC316
On page 12 the data sheet of the DDC316 states:
Table 1:
Range3 -> Input Range = –0.1876pC to 12pC
Table 2:
–1.7857% FS = 0x0000 with –1.7857% * 12pC = -0.214284pC
How should I understand the difference of the…
Part Number: DDC316 The data sheet of the DDC316 states (page 12 table 2) that input signals >=100% FSR will result in ideal output code 0xFFFF.
If an input is supplied with a current that slightly exceeds >=100%FSR the output code is 0xFFFF.
But…
Part Number: DDC316 Hello,
On one of my prototype boards, I experienced failure of one of the DDC316 components. It pulls an additional ~100mA at the 12V benchtop supply (which is stepped down to 3.3V and 5V through isolated power supplies), and gets…
Part Number: DDC316 Data on DOUTx are shifted out on rising edge of DCLK but on page 17 the datasheet states "Data are shifted out on the falling edge of DCLK." and the timing diagram "Figure 1. Serial Interface Timing" on page 6 also.…