Part Number: DLPC3433 Other Parts Discussed in Thread: DLP3010 We are trying to design a system that uses a DLPC3433CZVB, DLPA2005ERSLT, and DLP3010.
In order to set the thing up, we had to download firmware from TI.
There appears to be no ability to custo…
Part Number: DLPC3433
I am using DLPC3433 with these firmware settings:
After trying to communicate unsuccessfully with the address 0x36, I ran i2cdetect and found that the address for the DLPC3433 is 0x1B.
Why?
Part Number: DLPC3433 Other Parts Discussed in Thread: DLPA2000 , DLPA3005 , DLPA2005 , DLPA3000
Hi,
I'm having a strange issue while handling the power-on sequence in the Linux driver for DLPC3433.
My design has GPIO's for PROJ_ON, PARKZ, and regulators…
Part Number: DLPC3433 Other Parts Discussed in Thread: TIDA-080003 , DLP3010 In DLPC3433 Datasheet (Rev E) section 10.1 it mentions criteria for selecting a ferrite bead
I noticed in the DLP3010 reference design (tida-080003_dlp3010evm_LC_displayboard_revB…
Hello Morgan,
Thank you for providing the part numbers. These two DMDs, although similar, are meant for two distinct platforms. The DLP3010 is designed to be used with a DLPC3433/3438 controller for display applications. The DLP3010LC is meant to be used…
Hello Jagan,
The alternative video source that Philippe mentions above would be either a video generator or computer acting as a front end that would be connected to your display through an HDMI port. He has suggested this to determine if the video front…
Part Number: DLPC3433 Hi,
6.15 DSI Host Timing Requirements mentioned the range of HS Clock from 85 to 235MHz and the desired value would need to write it on Write DSI HS Clock (BDh) register.
Pixel Clock is the Panel or DMD side clock which is very much…
Part Number: DLPC3433 Other Parts Discussed in Thread: DLPA3000 Hello,
How can I create a custom firmware file for the DLPC3433?
I would like to adjust some of the battery management settings, splash screens, and maybe some other settings as well.
Is…
Part Number: DLPC3433 My team is having a hard time routing the MIPI data lines (from DisplayPort to DLPC) on one plane.
In order to match p/n lengths, we can get it down to 2 vias but not less.
Will this suffice or will 2 vias on a line cause too much…
