Part Number: DLPC3437 Do you have any example code available? Is there a python package or API available to control the DLPC3437? It only needs to be used to control the opening and closing of the device.
Part Number: DLPC3437 Other Parts Discussed in Thread: DLPDLCR3310EVM FPGA model: XC7Z020-1CLG484I4493
DDR3 model: MT41K64M16TW-107: J
DLPC model: dlpc3437
According to the 0.33 male board DLPDLCR3310EVM DISPLAY BOARD cable given by TI, the video input…
Part Number: DLP3310 Other Parts Discussed in Thread: DLPC3437 , , DLPC3439 , DLP4710 , DLP2010 , DLP3010 I am looking for verification that DLP3310 used with DLPC3437 can support 1080p @ 120Hz refresh rate. Can anyone at TI confirm this is possible and if…
Part Number: DLPC3437 Other Parts Discussed in Thread: DLPA3000 , DLPDLCR3310EVM Hi team,
we have some quesiton about DLPC3437 EVM
1. In the figure 4-1 of DLPC3437 EVM, there have a FPGA block. what's the function of FPGA?
2. Which firmware can provide…
Part Number: DLPC3437 Hi, Sir
currently, we have a new project, and want to get the sample code of FPGA for DLPC3437. So could you provide it.
Thanks
Zhang Tao
Part Number: DLP4710 Other Parts Discussed in Thread: DLPC3437 , DLPC3439 Tool/software: When I look at the driving data of DMD, no matter DLP330, DLP470 or DLP5530, their driving mode is basically the same. The SubLVDS signal of DMD lens drive is divided…
Part Number: DLP3310 Other Parts Discussed in Thread: DLP3010 , , DLPC3437 Tool/software: Hi,
As I know, DLP3010 DMD mirror resolution is 1368 x 768, DLP3010 is applied, application block diagram is like below picture.
There is a FPGA and FPGA receive…
Part Number: DLPC3437 In DLPC3437 Datasheet page 30, it says DLPC3437 support 1080P 48Hz 3D. How to set 1080P 48Hz 3D support in composer project? I only saw 720P/WXGA 100Hz/120Hz 3D are supported, no 1080P 48Hz 3D.
Hello Christopher,
Sorry for the delayed response but I discussed internally and have the following debug advice.
My suggestion would be to check power rails and signals throughout the path of communication to ensure all chips are powered up and see if…