• 

  Uryyy

  • 2 days ago
  • DLP® products
  • DLP® products forum

  DLPC910: Row Operations

  • Resolved

  Part Number: DLPC910 Old data sheet(DLPA092–January 2018) says New data sheet(DLPS064D) says
• 

  Fizix

  • 12 days ago
  • DLP® products
  • DLP® products forum

  RE: DLPC910: LVDS input termination (Datasheet Rev D)

  Hi Frank, There is no actual change to the design. It was discovered that this had not been properly implemented in the FPGA design. This was only a documentation stating that it is "required". If your design was working it should continue...
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  Fizix

  • 3 months ago
  • DLP® products
  • DLP® products forum

  RE: DLPC910: ECP2_FINISHED signal cann't go high （ECP2_FINISHED信号无法拉高）

  Hello again user, Do you still need assisatnce with this question? If not could you let us know how you solved it so others can benefit from your learning? Fizix
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  Uryyy

  • 5 days ago
  • DLP® products
  • DLP® products forum

  DLP9000X: Maximum length from DLPC910 to DLP9000X

  • Resolved

  Part Number: DLP9000X I think LVDS data length should be complied within 375mm as datasheet saying. However, I would like to know the background how is the MAX length decided as 375mm. Are there problems when more length is used?
• 

  Fizix

  • 3 months ago
  • DLP® products
  • DLP® products forum

  RE: DLP9000X: Minimum display time of 8-bit gray pattern

  Hello Zhiguang, Welcome to the DLP section of the TI-E2E forums. You are correct. However it does assume that you have a modulated light source. Also, there are no defined sequences in the DLPC910. You have to build an 8-bit grayscale sequence on...
• 

  Muthukumar Muthukrishnan

  • 5 months ago
  • DLP® products
  • DLP® products forum

  DLP9000X: Interface details of DLP9000X

  TI Thinks Resolved

  Part Number: DLP9000X I am planning to take up a projector project and wish to use your product DLP9000X. When I gone through datasheet of DLP9000X, it is understood that DLP9000X should be used with DLPC910 controller. It was also noted that interface...
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  Corey

  • over 1 year ago
  • DLP® products
  • DLP® products forum

  RE: DLPC910: Develop board test program

  Hello Fizix， Thanks for your help and please forgive me for not replying to you in time. I have found the problem and can write the program. After grounding one end of the resistor R64 and raising the DONG pin, FPGA burning can be realized. C...
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  Rossinag

  • over 1 year ago
  • DLP® products
  • DLP® products forum

  DLPC910: DCLKIN DLPC910

  • Resolved

  Part Number: DLPC910 Dear All, In our early development phase DLPC910 will be driving with 200MHz
• 

  Justin Chen14

  • over 1 year ago
  • DLP® products
  • DLP® products forum

  DLPC910: Not getting RST_ACTIVE after block mode operation

  TI Thinks Resolved

  Part Number: DLPC910 Dear all, Here is our flow: 1. After a power cycle, we assert the ARSTZ and wait until the INIT_ACTIVE to be deasserted. 2. We read the DESTOP_INTERRUPT (0x0000) register and the “bit 2” is 1. We then clear it as the...
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  Zan Zhan

  • over 1 year ago
  • DLP® products
  • DLP® products forum

  DLPC910: what is going to happen when DLPC is in idle

  TI Thinks Resolved

  Part Number: DLPC910 Hi I am concerned the content in 8.5.3 of DLPC910 datasheet as shown below "Disabling the watchdog is not recommended unless the user ensures that a mirror clocking pulse to the entire DMD occurs within 10 seconds...

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