Part Number: DP83867CR Hi,
As per datasheet, Reset_N pin is having a internal pull-up but Pull up value is not mentioned in datasheet anywhere. Please let me know about it.
Thanks
Sagar
Part Number: DP83867CR Hi all,
I would like to ask you the question about 8.6.35 Viterbi Module Configuration (VTM_CFG) register.
What is the meaning of this register?
My customer uses DP83867CR to develop the Encoder/Decoder.
Packet loss occured d uring…
Part Number: DP83867CR Other Parts Discussed in Thread: DP83869HM Hello TI Team
on DP83867CR we would like to use the PHY with the following modes:
RGMII to 1000Base-X in normal operation
JTAG for boundary scan during production
Now, OPMODE 1 and 2…
Part Number: DP83867CR Hi,
Our switch can have Inter Packet Gap as short as 72ns. It generates a lot of Rx errors that we can see in RECR 0x0015 and on the RX_ER signal form RGMII. When setting VTM_CFG register (0x0053) bits 3:0 to 0x4 (IPG < 12), we can…
Part Number: DP83867CR Other Parts Discussed in Thread: DP83869 , DP83867IR Hi,
In our new project, we need two DP83867 conencted through MDI interface. Does DP86837 support single cap isolation connection between one DP83867 and another DP83867? See the…
Part Number: DP83867CR Hi,
We are using DP83867 1G phy over RGMII with JETSON AGX orin and did following changes in dtsi. Please let me know it is correct or not-
ethernet@2310000 { status = "okay"; nvidia,mac-addr-idx = <0>; nvidia,max…
Part Number: DP83867CR How do the INT/PWDN and RESET_N pins need to be configured for proper JTAG operation? We believe the INT/PWDN pin needs to be held high for the JTAG controller to work, but what about the RESET_N pin? Does the JTAG controller override…
Part Number: DP83867CR Hi team, according to the datasheet the supply voltage with RGZ package is 1V:
The device is used on a board where only 1.1V is available (FPGA Core Supply). An additional regulator for the PHY should be omitted, so the 1.1V were…
