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Showing 623 results View by: Thread Post Sort by
    Answered
  • RE: DRA821U: How to use the main domain SPI under mcusw

    Long Jiang
    Long Jiang
    Resolved
    Hi, Erick After I update the sbl it works! I used to think that just by changing the app, the clock can be enabled, because the app run AppUtils_Init(), but I didn't expect it to be initialized in sbl. This resolves my issue. Thanks. Regards, jiang…
    • 21 hours ago
    • Processors
    • Processors forum
  • RE: DRA821U: How to reset A core/Linux individually?

    Kevin Lavery
    Kevin Lavery
    Yong, Suppose that you have an error in one of your cores. What did the software do?? In that case, I'd think that you'd have to assume that your memory was invalid. If you are looking for a way to reset only the A72 from the MCU R5F, you will want…
    • 9 days ago
    • Processors
    • Processors forum
  • RE: DRA821U: programming OSPI FLASH from DRA821 CPU via JTAG

    Karan Saxena
    Karan Saxena
    Hi, Re-posting my old response, somehow I don't see that on the forum now. Zeev Gerber said: I tried to program Flash device on Evaluation board (TI Jacinto 7 J721E) using Blackhawk USB560v2 Trace Emulator ( https://www.ti.com/tool/TMDSEMU560V2STM-…
    • 17 days ago
    • Processors
    • Processors forum
  • DRA821U: PWM signal sample abnormal

    terry si
    terry si
    Part Number: DRA821U Hi I used ICU model to sample PWM signal. It works perfect in the most of time, however, the sample result turns a 30% deviation when the sampled signal keeping the same. The sample result soon became normal in next 2 or 3 sample…
    • 1 month ago
    • Processors
    • Processors forum
  • RE: DRA821U: SGMII compliance with 100BASE-T

    ShreyasRao
    ShreyasRao
    Hi Jack, Yes, I have received it over email, and is being looked into. The SGMII communicates at 1G link speed even during 10/100M mode. We are waiting on the CPSW stats before and after the test to determine the errors. The same 1G SGMII configurations…
    • 29 days ago
    • Processors
    • Processors forum
  • DRA821U: Processors forum

    Deyin Zhang
    Deyin Zhang
    Part Number: DRA821U Other Parts Discussed in Thread: DRA821 DRA821 BSDL file (J7200_DRA821_v1p0), DDR_RET signal PIN must be low level to enter BSDL function. According to the DEMO reference provided in 2021 (tidm738_SCH), H_DDR_RET_1V1 requires pull-up…
    • 1 month ago
    • Processors
    • Processors forum
  • DRA821U: ABOUT PM A CORE

    Cherry Zhou
    Cherry Zhou
    Part Number: DRA821U Other Parts Discussed in Thread: DRA821 Hi team, With regard to DRA821 power management, there are important applications (RTOS) deployed under the R core of the main domain. Is there A single SOLUTION for A core reset (Linux reset…
    • 1 month ago
    • Processors
    • Processors forum
  • RE: DRA821U: cpsw5g VLAN configuration

    Swapna yendrapalli
    Swapna yendrapalli
    Thank you! please update this thread when you have more information.
    • 1 month ago
    • Processors
    • Processors forum
  • Answered
  • DRA821U: About the RHR_IT_DIS bit in the UART_IER2 register

    tomitama
    tomitama
    Resolved
    Part Number: DRA821U Other Parts Discussed in Thread: DRA821 About the RHR_IT_DIS bit in the UART_IER2 register Does DRA821 have a RHR_IT_DIS bit in the UART_IER2 register? If so, what is the function of the RHR_IT_DIS bit? The RHR_IT_DIS bit is listed…
    • Resolved
    • 1 month ago
    • Processors
    • Processors forum
  • Answered
  • RE: DRA821U: Restriction of GPMC bus connection mode

    Parth Nagpal
    Parth Nagpal
    Resolved
    Hi Toshiya, Toshiya Asai said: So, I think that GPMC non-multiplexed mode of DRA821U is almost unuseful. Is this correct ? Looking at the response in https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1018717/dra821u-gpmc0_a16-and…
    • 1 month ago
    • Processors
    • Processors forum
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