Hi Swapna,
In the kernel can you try reverting the below:
commit de04540ad08719381d37e574895c8f7bc10f53ef (HEAD -> ti-linux-6.1.y)
Author: Vaishnav Achath <vaishnav.a@ti.com>
Date: Thu Feb 22 11:58:55 2024 +0530
Revert "spi: cadence-quadspi…
Part Number: DRA829V
Hi,
We've received the following question from my customer. Could you answer this inquiry ?
When comparing tifs.bin files with the same name between PDK8.5 and PDK9.1, the contents are different. What is the difference?
I am comparing…
Part Number: DRA829V
Hello TI,
in thread https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1321380/dra829v-ospi-flash-controller-for-qspi-device-mt25qu02g/5035545#5035545
I did find the information that base address of OSPI1 Module…
I see USB HUB team has answered question regarding reset requirements for their device:
TUSB8041: Glitch on reset during power on - Interface forum - Interface - TI E2E support forums
Part Number: DRA829V
Dear TI team,
My name is Jakob and I am working on a MCAN driver. I was not able to find more detailed information about the following registers:
MCANSS_ECC_SEC_STATUS_REG0
MCANSS_ECC_DED_STATUS_REG0
Both with the following fields…
Part Number: DRA829V Posting on behalf of Kenley -san
Could you please check the attached file about the sciclient build error?
Sciclient_BuildError.xlsx
Kenley
Summarizing discussion from over email. Thanks to Richard.
#1: The MMSC3 is a system cache which can be used by SOCs in the system. To allocate in it the write-back + alloc + shared setting needs to be set.
#2: The R5 can allocate into the MSMC3…
Part Number: DRA829V
Hello experts!
I'm setting up a build system for colleagues to work on the r5f cores on this SoC. I have a custom board that is built upon SDK 8.6. I have downloaded the latest RTOS PDK version 09_01_00_06.
Building the echo tests…
Part Number: DRA829V Hello,
I was looking into the CSL RTI example from the j721e 8.6.1.3 PDK.
I saw on this family of devices that resets from the RTI were not supported.
I have two questions
1) Is the interrupt routed in this way considered a FIQ…
Hi Rajashekar,
I am currently going through some old threads that are open. Apologies for the delayed response and let me know if this thread can be closed.
I assume this is related to the other E2E thread here: https://e2e.ti.com/support/processors-group…