Part Number: LM3880-Q1 Hi
On the datasheet, it is mentioned that there are 120ms period at incomplete power-down sequence.
1. What is happen if EN is asserted at that 120ms period? Do this device accept the EN assertion at that 120ms period?
2…
Other Parts Discussed in Thread: LM3880 Hi all Would you mind if we ask sequence? Our customer would like to make power up sequence in case of Vin=12V. There is no Power Sequencer which is avilable for Vin=12V. LM3880 is not avilable for Vin=12V.(MAX…
Hi Koji-San
Please refer the DS 8.3 Do's and Don'ts. It also list some recommends circuit.
During power-up, the EN voltage should be kept below the EN threshold until VCC rises above the minimum operation voltage.
Hope this helps.
Regards
yihe…
The abs max on the FLAGx output is 6.0V. This design would involve pulling this up to 7.0V through a 67K ohm resistor. This would result in a very current limited pull-up bias. This 1.0V above abs max would result in a worst case bias current of 15uA…
Part Number: LM3880-Q1 Hi
Is there any limitation of EN pulse width?
The FLAG does not response if the small pulse of EN signal(High or Low) which is smaller than delay time is input.
Regards,
Koji Hamamoto
Hi Mathew,
Please let me ask one more question.
I tried to change Enable from low to high after FLAG1 went low, then I could not see incomplete power down and also could see power up after fixed duration after EN low. The duration is not specified…
Other Parts Discussed in Thread: LM3880 Hi, Could you tell me about LM3880 Flag pin voltage? I have attached the waveform that is happening is a problem. Is there a way to improve the phenomenon in which a little the voltage rises? LM3880.pdf
Best regards…
