Hi Norikazu,
I have checked the settings for page0, address 0, bit 2, 4, and 5, and tried different combinations, but the situation doesn't seem to have improved. Is there any other possibility? Can the LM98725 maintain high-speed line…
Part Number: LM98725 Tool/software: Team, My customer is facing LM98725 noise issue on AD conversion result of OSx as the picture below. There is 10-20 LSB glitch in the middle of the plot, but OSx is almost flat like blue trace of the picture below. Please…
Part Number: LM98725 Other Parts Discussed in Thread: LM98620 , LM98519 Hello Sir:
Our competitor is WM8234.
https://www.mouser.tw/datasheet/2/76/WM8234_v4_8-3078666.pdf
Can you recommend a suitable solution for us?
Looking forward your feedback.
Thanks…
Part Number: LM98725 Hello team,
I received a question from the customer.
The customer thinks that there is no specification in the datasheet for the time from power ON to start communication via Serial Interface, but is it OK to start serial communication…
Part Number: LM98725 I have one Question. I am using CMOS ouput.
Look at the picture.
Yellow is PHIA1, Blue is SH2 (ADCCLK) , Red is DOUT4, Green is DOUT7.
CIS SP(Start Pulse) is PHIB1, CIS CLK is PHIA1.
[Page 8, ADDR 0x00, [6] Bit is 0] , [Page…
Part Number: LM98725 Other Parts Discussed in Thread: DS90CR218A Hi all,
I want to use LM98725 for CIS sensor.
Can LM98725 be used for CIS Sensor?
I want to use STM32H723xx. (MCU)
I want to use LM98725 via PSSI pin (MCU function).
I don't know that How…
Part Number: LM98725 Hi team,
A question from one of our customers:
The LM98725 is 8bit*2 in CMOS output format, the customer docks a chip that is an 8-bit DVP interface, but the software does not allow sampling eight bits MSB and eight bits LSB on the…
Connect SIG1/2/3 pins with OSR/G/B then Analog to Digital converted result of each pin will be transferred to backend controller through LVDS. Backend controller needs to process each signal.
Best regards,
Norikazu Takebayashi
Part Number: LM98725 Hi support team.
Would you please provide the information that the latency from SH_R_rescync(SH_int) rising edge to SH interval rising edge as TBD in DS P56(fig.37) - P60(fig.41)?
Best regards,
Higa