Part Number: ADC08060 Other Parts Discussed in Thread: ADS831 , LMK01010 Hello
What are the solutions for sampling clock generation of single/multiple mid range high speed converters like adc08060 or ads831 with\out phase shift?
Thanks.
Hi Mickey,
Here are a few suggestions that fit your criteria, listed with best additive jitter performance first:
1. LMK01010
-1:8 LVDS out, 1600MHz max
-30fs additive jitter
-Individual output enable via register programming
2. CDCUN1208LP
-1:8 LVDS…
Other Parts Discussed in Thread: LMK04828 , LMK01010
Hi team,
Please advise me on archiving the best jitter performance using LMK04828. I tried to archive the best performance generating 80MHz clock from jittery 10MHz reference clock. When I checked the…
Other Parts Discussed in Thread: LMK01020 , ADC08D1520 , LMK01010 , LMK01000 Hello,
I want to use LMK LVPECL CLK BUF at 1.5GHz to clock the ADC08D1520. ADC08D1520 has a CLK+/- input range of 0.4Vpp<Vid<2.0Vpp and LMK01020 datasheet (on page 7/26 of LMK01000…
Part Number: LMK00101 Other Parts Discussed in Thread: LMK00301 , LMK04808 , LMK01010 , LMK01020 Hello,
We are in the process of designing a multi-channel data acquisition system. The ADCs will be spread across several (8 at the moment) daughter boards…
You are right, Dean. I have reinstalled CodeLoader and everyting is working OK. The *.mac file I generated yesterday was corrupted too and when I load it, even with the new installation, all the addresses are set to '0000'. I have generated it again and…
Hello Jim,
I have a question regarding the part 5.0 (Reset using ADC CLK start/stop method) of the PDF file you addressed in your last post, which seems to be an easier way to synchronize multiple ADC08D1520's (3x in my case).
I have a low jitter…
Hello Praveen,
In the attach PDF I try to show a possible solution for a clock distributions from crystal source through TI LMK03000 and LMK01010 Timing products to the LM96570 and FPGA , plus synchronization Reset implementation .
1385.Reset c.pdf