Part Number: ADS54RF63 Other Parts Discussed in Thread: LMK01020 , Hi,
I am using ADS54RF63. The device is working fine at 200 MHz. But when I am operating at 400 MHz, the data is getting corrupted at ADC pin itself. I am using LMK01020 for clocking and…
Other Parts Discussed in Thread: LMK01020 , LMK01000 Hi,
I'm using lmk01020 for distributing 550 MHz and its div2 for using 3 samples of each frequencies. My question is about additive jitter due to using divider relative to only distribution path and of…
Hello Jim,
I have a question regarding the part 5.0 (Reset using ADC CLK start/stop method) of the PDF file you addressed in your last post, which seems to be an easier way to synchronize multiple ADC08D1520's (3x in my case).
I have a low jitter…
Part Number: LMK00101 Other Parts Discussed in Thread: LMK00301 , LMK04808 , LMK01010 , LMK01020 Hello,
We are in the process of designing a multi-channel data acquisition system. The ADCs will be spread across several (8 at the moment) daughter boards…
Other Parts Discussed in Thread: ADC07D1520 , LMX2541 , LMK01020 , LMK04808 I need some help choosing the best solution for a 1:4 1 ,500 MHz clock distribution system, that will feed 4 ADC07D1520 chips. The 1,500MHz are generated by a LMX2541 from a 100MHz system…
Other Parts Discussed in Thread: ADC08D1520 Hello,
I have 3 questions and wondering if you can help me to find out the answers
1- I am musing 3 ADC08D1520 in my design and would need to know as the worst-case scenario how much sampling between 3 ADC's…
Hi Satoshi,
If you want to get a 80MHz differential clock output from a 640MHz clock input, I suggest use clock buffer instead of PLL synthesizer.
For example, LMK01000, LMK01010, LMK01020, CDCE18005, CDCM1802, CECM1804, CDCP1803. These clock buffers…