Part Number: LMK04805 Please tell me how to readback all registers listed in table.16 in the datasheet.
※ LMK04805 datasheet
<www.ti.com/.../lmk04805.pdf
Part Number: LMK04805 Hello,
In LVDS mode of the LMK04805, If the receiver device has an internal 100 ohm termination resistor, is it okay to remove the external 100ohm termination resistor?
Thank you.
JH
Part Number: LMK04805 Other Parts Discussed in Thread: CODELOADER Hello,
My customer found that the polarity definitions of 5 and 6 values of SYNC_TYPE(R11[14:12]) define differently between the datasheet and the clock tool(CodeLoader, TICS).
Which definition…
Part Number: LMK04805 We are using the LMK04805 with a CVHD950 122.88MHz VCXO and a 30.72MHz TCXO, then we set the output divider of clock out 0 to 1, so we have 2293.76MHz at the output. Phase noise looks ok above 10Hz. But on the spectrum analyzer we…
Part Number: LMK04805 Dears.
We have used LMK04805. I am testing with LMK04805EVM. I entered 122.88Mhz into REF Clock(CLKin1) and set the GUI as follows. 122.88Mhz is supplied as a Signal Generator. Lock does not work. Why can not I lock?
Thank you
…
Part Number: LMK04805
Hi team,
Can you confirm that R26[27:26] in LMK04805's datasheet is for PLL1_CP_GAIN, or PLL2_CP_GAIN? If it's a typo, can you please fix the datasheet?
Thanks and Best Regards,
Sam Lee
Hi,
The evaluation board users guide for the LMK048xx family of parts: www.ti.com/lit/snau076 has a phase noise plot down to 10 Hz using a VCXO from Crystek
You should be able to simulate LMK04805 output clock phase noise performance using a commercial VCXO…
Hi Doug,
The least common multiple of 150 MHz and 125 MHz is 750 MHz, so you will need a multiple of 750 MHz to generate both frequencies. There is no multiple of 750 MHz in the 2370-2600 range. So your assumption is correct, the VCO range on the LMK04816…
Part Number: LMK04805BEVAL Other Parts Discussed in Thread: CODELOADER , LMK04805 Hello all,
i am trying to get synchronized input and output clock from LMK04805 (0-delay mode) but without success. I am using codeloader and set dual PLL,Int VCO,0-delay…
Hi Jaime Martin,
Here is a better comparison. The reference is a 100 MHz WENZEL
But to your point, you are absolutely correct. If you are driving LMK04805 PLL1 configured for relatively low bandwidth, the broadband noise floor is irrelevant. Either buffer…