Part Number: LMK04826 Other Parts Discussed in Thread: LMK04828 , ADC12DJ5200RF , LMK04821 Hi Team,
My customer is using LMK04826 provide JESD204C REFCLK for FPGA , but got some problem with JESD204B link,
1. The original design(ref. to picture…
Part Number: LMK04826 Hello,
How can I get a LMK04826 into a low-power condition? The power consumption of a system where the LMK04826 is used is required to be as low as possible when the system is in an idle state.
Besides, how much will the current…
Part Number: LMK04826 Other Parts Discussed in Thread: LMK04832 , LMK04832EVM Dear Sir/Madam,
We are intend to use LMK04826BISQ/NOPB device in our product, We have some following query
1. Can we able to generate 250M Hz Clock for the FPGA.
2. Can…
Part Number: LMK04832 Other Parts Discussed in Thread: LMK04828 , LMK04826 , , AFE58JD48 Team,
LMK04832 is out of stock. We have to consider the replacement for short term. I remember LMK04828 and LMK04826 are used for AFE58JD48/28EVM.
Are these…
Part Number: LMK04826 Hello,
My customer had intermittently an issue with JESD link error during device initialization.
The device's REFCLK and SYSREF clocks are both provided by the LMK04826.
The have found that changing the LMK04826 register 0x143…
Part Number: LMK04826 Hi team,
Customer puts forward some question. Would you please help me to answer Thanks a lot.
The holdover function of the LMK04826 has the following questions: 1. Where to set the entry and exit conditions of the hold state…
Part Number: ADS52J90EVM Other Parts Discussed in Thread: LMK04826 , ADS52J90 Hi
I would like to get 16ch-12bit-76.8 MSPS data with ADS52J90EVM
It needs two 76.8 MHz device clocks and two19.2 MHz sysref clocks.
I want to generate the clocks using…
Part Number: LMK04826 Other Parts Discussed in Thread: ADC12DJ3200 , LMK04828 , LMK04832 , LMK04808
Question,
If trace lengths are matched, what are the correct delays for two pairs of DEVICE and SYSREF clocks going to an FPGA JESD block and the ADC12DJ3200…
Part Number: LMK04826 Hello,
My customer is considering using 'Tracked CPout1 Holdover Mode'.
To enable this feature, they set the LMK04826 as shown below.
2664.lmk04826.dat
After unlocking PLL1 by tilting the reference clock frequency, they read…