Hello Matthew,
That is correct, the maximum Vin voltage would be 3V in this case. However, the LMK1C1108 would work, as shown in this statement from the data sheet:
Best,
Andrea
Part Number: LMK1C1104 Other Parts Discussed in Thread: LMK1C1108 Tool/software: I am looking for an alternative for LMK1C1104DQFR. I need higher output current and faster rise time.
Please let me know if you have a device that meets these needs.
Part Number: CDCM6208 Other Parts Discussed in Thread: CDCEL949 , LMK1C1108 Tool/software: Hi,
Please recommend a TI clock driver with the following requirements:
(1) Input channel number: 1, output channel number: 8;
(2) Operating frequency: 72MHz; …
LVDS repeaters are designed for LVDS signals.
There are clock buffers like the LMK1C1104/LMK1C1108. But you could also use plain logic buffers like the SN74LVC125A/SN74LVC541A/SN74AHC125/SN74AHC541/SN74LV125A/SN74LV541A.
Part Number: LMK1C1104 Other Parts Discussed in Thread: DP83869HM , , LMK1C1108 Hi Everyone,
Clocking Architecture for DP83869HM Ethernet PHY:
In my design I have 14 Ethernet Interfaces. 10 was configured as 1000BASE-T and 4 was 100BASE-TX.
For that…
Hi Ivy,
The LMK1C1108 has 8 LVCMOS outputs and a part-to-part skew of 250 ps, which is currently the best available out of our single-ended output buffers. If a differential output format is ok, then the LMK00334 or the LMK00308 can reach a typical part…
Hello Katsuyo,
The graph represents the power consumption when all outputs are enabled for the LMK1C1108.
The Zo is the trace impedance of the trace connected to the output. It is equivalent to a 50 ohm resistor.
Regards,
Kia Rahbar
Part Number: ADS127L01 Other Parts Discussed in Thread: LMK1C1108 Hello
1. Is it possible to cascade 6 ADCs (ADS127L01) in frame sync mode?
One frame sync master mode ADC outputs FSYNC (500 kHz) and SCLK (16 MHz) signals to 5 ADCs (and one FPGA) input pins…
