Part Number: PCM1808-Q1 Other Parts Discussed in Thread: PCM1808 Hi team,
I have a question about the data format of PCM1808 in FORMAT=Low setting below.
#1. How many BCLK cycles or DATA bits in 1 LRCK cycle?
#2. Does DOUT hold the last data value…
Part Number: PCM1808-Q1 Other Parts Discussed in Thread: PCM1808 Hi Team,
I use PCM1808 in slave mode. And input SCLK=256fs,BCK=64fs. If change sampling rate 48kHz to 44.1kHz (change SCLK 12.288MHz to 11.2896MHz too,)
･How many sec does it take from…
Part Number: PCM1808-Q1 Other Parts Discussed in Thread: PCM1808 , Hi team,
Is there test mode (debug or trimming purpose) in PCM1808?
I concern if it accidentally fall into that mode during operation.
regards,
Part Number: PCM1808-Q1 Hi team,
I plan to use PCM1808-Q1 slave mode system clock = 12.288MHz (48khz, 256fs).
Could you give me the rise time and fall time requirement for this clock input?
regards,
Part Number: PCM1808-Q1 Other Parts Discussed in Thread: PCM1808
Hi team,
If signal is present on ADC input during device power up timing, does PCM1808-Q1 may output noise on DOUT?
I concern if PCM1808 output noise during "Zero Data" below when…
Part Number: PCM1808-Q1 Hello,
My customer was wondering the BCK in slave mode from the description on page 14 in the datasheet which says :
Slave mode In slave mode, BCK and LRCK work as input pins. The PCM1808-Q1 accepts 64-BCK/frame or 48-BCK/frame…
Part Number: PCM1808-Q1 Hi team,
Could you give me comment on following customer question on connectivity to DSP?
Q1. Can PCM1808QPWRQ1 be connected to C6742/46/48?
Best regards,
Takeshi Sasaki
Part Number: PCM1808-Q1 Other Parts Discussed in Thread: PCM1808EVM Hello Team,
PCMM1808-Q1 has AGND, DGNG pin which need to connect with Ground.
Q. Do you have any recommendation how to design the layout pattern. Example layout is very helpful for…
Part Number: PCM1808-Q1 hello, in the current design, there is a possibility that only VCC is applied and no VDD present, is there any issue? device may damaged or anything?
