Part Number: PCM3168A Other Parts Discussed in Thread: PCM3168 Hello,
PCM3168A is configured TDM8 output, combined LRCKAD and LRCKDA to connect LRCK of host. Combined BCKAD and BCKDA to connect BCK=12.288M of host, SPI mode,PCM3168 is used as slave ,sample…
Part Number: PCM3168A Hi
Can 10 uF ceramic caps be used on the VCOMAD, VCOMDA and VREFAD1/2 outputs?
The datasheet recommends electrolytic caps, but we would prefer to use ceramic caps.
If a higher ESR cap is required, we can add series R's to the ceramic…
Part Number: PCM3168A Other Parts Discussed in Thread: PCM3168 Hi,
I'm in a project where I need to have 6 different audio communication paths. I need each channel to be able to establish calls to one or several sip phones.
In A, i have an analogic…
Hi Pdjuandi,
pdjuandi said: Try triggering on SCKI
Customer would like to know how to trigger on SCKI? Disconnect LRCLK from BCLK, only let SCKI output the signal, and then observe LRCLK/BCLK?
Thanks,
Annie
Part Number: PCM3168A Hello,
One customer used PCM3168A and met questions, he combined LRCKAD and LRCKDA to connect LRCK of host, combined BCKAD and BCKDA to connect BCK=12.288Mhz of Host. SPI mode, sample rate LRCK:48K MCLK: 12.88M, BCK:12.288M. Reading 0x51…
Part Number: PCM3168A Good day I would like to make full use of all ADCs and DACs on the PCM3168A in slave mode. The master in this case can only provide one bit clock and it would be a preference to connect it to both clock pins. Would there be any undesired…
Part Number: PCM3168A Other Parts Discussed in Thread: TLV320AIC3262 Hi,
I'm not expert in audio, so I need help to clarify my doubts.
I'm developping a project which I have a central unit (A - where I have a micro, internet connection, etc) where…
Hi Shifali,
The analog input level is the voltage value of the analog signal applied at the input, while full scale input voltage is the largest signal amplitude that can be delivered to the analog to digital converter before the signal is clipped in…
Part Number: PCM3168A Hi,
I am using PCM3168APAP in my design. I am using 6 audio input and 4 audio outputs in my design. The clock frequency details are as below:
LRCK - 48kHz SCLK - 3.072MHz MCLK - 12.28MHz
Will the IC introduce any default delay between…