Other Parts Discussed in Thread: PCM4222 Hi I am using the PCM4222 TDM slave mode and the is a one BCK period delay on the data, the FMT1 and FMT0 are set correct( if you set them both Hi you get another delay). In master mode the data is correct - no…
Hi, Shawn,
The overflow flags of the PCM4222 are used to indicate whenever a digital overflow event is detected. This might occur when the analog input exceeds the full scale voltage spec, that is 5.6Vpp for each differential input pair (or 2.8Vpp…
Hi, Okko,
Welcome to E2E, Thanks for your interest in our products!.
The different speed modes featured in this device are optimized to get the best performance for each sample rate by selecting the proper oversampling and filter combination. Using…
Other Parts Discussed in Thread: PCM4222 Hi All,
Is there a problem with the PCM4222 ADC when it runs at 96KHz? Apparently it is more noisy?
Could you help me solve this issue with a solution?
Thanks,
Jack
Part Number: PCM4222 I'd like to know if each pin from a stereo channel input pair (VIN) with 2.8Vpp has 24 bits of resolution and not the whole channel 5.6Vpp and if it's that true the size of payload data from a sample in the left justified communication…
Part Number: PCM4222 When using the TDM8 mode and paralleling up 4 PCM4222 ICs, do I require additional clock buffering per IC or can I just parallel these inputs?
I will use the front end circuitry from the EVM schematics which utilises the CLK source…
Hi Justin-san,
I know you are busy, however could you please let me know "LRCK Set up Time / Hold Time to BCK Rising Edge" for PCM4222 since we should inform our customer of it ? Your quick response would be greatly appreciated.
Best regards, Kat…
