Dear Sanjay:
We followed I2C command in the PCMD3180 spec and its CLK rate is 100KHz.
Then we tested SLEEP_CFG register (register address:0x02) by I2C reading and writing command.
First we writed 0x81 to address 0x02 and read the 0x02 address.
We can…
Part Number: PCMD3180 Hi team,
Could you help below?
Thanks!
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The PCMD3180 connects 3 microphones and set to TDM slave mode.
There is noise above 8kHz.
How to set the filter…
Part Number: PCMD3180 Hi,
I am posting this on behalf of my team working on a project that involves the recording of ultrasonic sounds using a mems microphone (SPH0641LU4H-1), and PDM to I2S translation of the audio output with the PCM3180. I read in…
Part Number: PCMD3180 I tried to simulate the signal integrity on the clock and data input and output. But I could not find the SPICE model of this part. The link for simulation is only for PSPICE software itself. My question is where I can find the model…
Other Parts Discussed in Thread: PCMD3180 Dear Ti member,
The input clock setting now we use is 24.576 MHZ ( 24.576MHz / 48kHz / 16 slots / 32 bits (32x16x48kHz=24.576MHz).) with two PCMD3180.
We are try to set some register to output the PDMCLK on PCMD3180…
Other Parts Discussed in Thread: PCMD3180 Dear TI member,
We're try to buring-up two pcmd3180 for 16 channels TDM output.
Now, it seem only one pcmd3180 TDM out put as below:
Green signal was TDM output.
Yallow signal was FSYNC from SOC.
Then I check…
Part Number: PCMD3180 Hi team
My customer Lango use PCMD3180 for advertisement display microphone, I need PPC3 software to generate the startup configuration and debug. Can you accelerate my request approval?
Thank you
Joe
June 14
Part Number: PCMD3180 Is AVDD feeding only the PLL? If I want to build the ultimate low power PCMD3180 design, and am willing to turn off the PLL and ensure my clock divisors work, can the power draw on AVDD go to zero? Thanks, Chris