• RE: TPS544B20: Schematics verification

  

  Naveen HN

  Peter, Below are few more observations: 1. CNTL is at 3.3V on pin 1 of regulator. 2. Pin 13 AGNDSNS and 38 AGND are kelvin connected in Layer 6 as shown in the attached image. 3. One thing to point is that the PGND is connected to AGND (which should not…

  • over 4 years ago
  • Power management
  • Power management forum

• RE: About FPGA power reference design

  

  JohnFullilove

  Hello. We do have some Power supply reference designs for Kintex Ultrascale FPGAs (PMP10630, PMP10555, PMP9463, PMP9444), however, I don't see one specifically for the XCKU15PFFVE1517 that you reference. I will check our with our Power Supply Design…

  • over 6 years ago
  • Power management
  • Power management forum

• RE: Xilinx Zynq Ultrascale+ TI Power Design

  

  Akash Patel

  A few TI designs that were found: http://www.ti.com/tool/PMP11328 and http://www.ti.com/tool/PMP10555

  • over 8 years ago
  • Power management
  • Power management forum

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