Hi Andrew,
1. LVDS line driver enable means CMOS data applied at input connector P2 is converted to LVDS and applied to the DAC's input.
2. When input CMOS data is applied at connector P2 and W3 is set to 2-3 enabling the CMOS data's conversion into…
Other Parts Discussed in Thread: SN75LVDS386 , SN65LVDS389 , SN65LVDS387 In the search for wide LVDS receivers for clock frequencies up to 312 MHz, I have come to a surprising fact that has confused me. Parameric table uses the concept 'signaling rate',…
