Part Number: TLV320ADC3100 Other Parts Discussed in Thread: PCM1862 Hi Sir,
I checked ADC3100 d/s looks can only set to 2 Differential mode(IN2L and IN3L, IN2R and IN3R), or 4 single end(IN2L,IN2R,IN3L,IN3Rsingle end).
If possible set to 1 Differential…
Part Number: TLV320ADC3100 Hi team,
Customer only uses IN3L and IN2L, just to make sure they need to connect a capacitor from IN2R/IN3R to ground, right? Can they use 0.22uF?
What if they leave these 2 pins open?
Thanks!
George
Part Number: TLV320ADC3100 Hi
Can you help share an example for TLV320ADC3100 initialization
below is our configuration
1. Single end Left channel audio line in from IN2L(P) pin 7
2. Single end Right channel audio line in from IN2L(P) pin 7
3. IN3L(M) an…
Part Number: TLV320ADC3100 Hi Sir,
Could you advise how to config the registers about the following setting?
MCLK is 24.576Mhz, BCLK is 3.072Mhz and Fs is 48K.
Thanks, Ian.
Hello,
Sorry for the long delay.
So you inserted the module with insmod and the CPU crashed? The dump does not really offer any information.
A lot of these drivers are ALSA based and require mapping at DTS along with a sound card. I have not inserted them…
Part Number: TLV320ADC3100 Hi,
Could you please tell me whether TLV320ADC3100 can work normally if using TLV320ADC3100 in the following conditions? In particular, I would like to know whether fs x 32 can apply to BCLK.
Conditions - Master Mode - MCLK = …
Hello Cary,
I see that you are unmuting the Left PGA but do not see the Right PGA unmuted (Register 0x3C). Please unmute this and write 0x32 to match the Left ADC.
Let me know if this helps.
Regards,
Aaron
I supplied 1.8 volt to DVDD and 3.3 V to IOVDD from an externally generated supply. Tested at 31.2Khz, with 1Khz AC signal of 200mVrrms 500mV offset and a coupling capacitor of 2microF.
Also tried without the coupling capacitance same results.
Output…
Part Number: TLV320ADC3100 Other Parts Discussed in Thread: TLV320ADC3101EVM-K Hi,
My question has two folds : a) This register : 8.6.2.28 Register 36: ADC Flag Register has bits highlighting that : for Left/Right ADC PGA, applied gain ≠ programmed gain…