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  • TMS320F28375S: TMS320F28375S

    • Resolved
    Part Number: TMS320F28375S Hi, All, As the function block of TMS320F28375S ，it has six pins for eCAP

  • TMS320F28375S: Difference between C2000 and Hercules microcontrollers

    • Resolved
    Part Number: TMS320F28375S Hi, At multiple places, I have read that C2000 microcontrollers

  • TMS320F28375S: Unable to observe Busy in CAN IFxCMD

    Part Number: TMS320F28375S In the TRM it describes that the Busy indication is set to '1' for a period of 4 to 14 clock cycles while there is a transfer between the Interface Register and the Message RAM. We are trying to see this condition set...

  • TMS320F28375S: The maximum value of Ivdd at power up

    • Resolved
    Part Number: TMS320F28375S Hi experts, The data sheet lists a range of recommended capacitor values

  • RE: TMS320F28375S: Controller failure

    Naveen Kumar reddy Nelavoy 1. As VREFHI > VDDA for 120usec, to simulate the condition we have used power cycles as test procedure in which there is no failure observed. But if we do a static test it might fail but can we relate to our failure scenario...

  • TMS320F28375S: how to get configuration for SPI CLK Active high and latch on the falling edge

    • Resolved
    Part Number: TMS320F28375S Dear SIr, we are developing controller based on 28376S and have some

  • RE: TMS320F28375S: How to configure EPMWx module such that EPWMxA is enabled and EPWMxB is disabled?

    You have the deadband module enabled. This will always override the EPWM outputs. Seems that you have complementary mode enabled.

  • RE: CCS/TMS320F28375S: HRPWM clarification needed

    EPWM 1 to 8. You can use any of the GPIOs that support EPWMxA, EPWMxB (x = 1 to 8). Nima

  • TMS320F28375S: What is the result if the input of CLAcosPU() is out of [-1,1]?

    • Resolved
    Part Number: TMS320F28375S Hi, I'm using CLAcosPU() in CLA and just curious about the input

  • RE: TMS320F28375S: TMS320F28375S: SYSCLK Frequency Check fails in some configurations

    Hi Jordan, We currently do not have this note anywhere, but we will add this in the next release. Their is no restriction from system side on running SYSCLK as low as 2 MHz, but for validating PLL frequency we have to use Timer2 and hence this constraint...

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