Part Number: TMS320F28386D Tool/software: Hello,
We are trying to reset all Core on the TMS320F28386D by sending a debugger (CPU1.SYSRS)
Once we reset all cores, CPU1 PC is at 0x03FD2AE , CPU2 and CM are held in reset.
Releasing CPU1 from reset…
Part Number: TMS320F28386D
Tool/software:
Hello, I have been working on the TMS320F28386D device and have some question I could not find in the different documents available to the public.
The TRM details that the MSGRAM X to Y and Y to X are…
Part Number: TMS320F28386D Tool/software: Hello,
I am currently working on the TMS320F28386D would need to know the inner mechanism of the SRAMs to determine their potential interference in a multicore environment. For all SRAMs and memories, do they…
Part Number: TMS320F28386D-Q1
Tool/software:
Hi TI experts,
As mentioned in the title, when our product is applied in the customer's vehicle, the CM core of the DSP encounters a CMNMIWDRSTn issue. This is a discrete probability event. When the problem…
Part Number: TMS320F28386D
Tool/software:
Hello,
While analyzing the TMS320F28386D design, I found multiple inconsistencies in the TRM about interrupts. Could you clarify the following information? What are the CM_RAM_TESTERROR_LOG, CIPC, MPOST…
Part Number: TMS320F28386D Hello,
I have questions related to the SFO library to calibrate the HRPWM.
As we are under aeronautical constraints, we can't really integrate a library without knowing what's inside it. I contacted our FAE before Christmas…
Part Number: TMS320F28386D Hello Experts,
This application uses a TMS320F28386
I am trying to run a filter algorithm in the CLA that requires long doubles (64-bit floats). The macro to run this is as follows:
#define RunFilter( Filter, InputData…
Hello Ozan,
I'm sorry for the delayed response; the original owner is no longer available.
Please look at the following documentation provided by TI regarding selecting and designing an appropriate ADC voltage reference source.
Voltage-reference…
Part Number: TMS320F28386D Hello,
I would like to know what would be the maximum number of cycles penalty when two CPU (or CLA/DMA) are accessing a shared resource such as GSRAM, message RAM or peripheral bridges ?
Are we talking of one cycle or could…
