Part Number: TMS320F28388D Other Parts Discussed in Thread: C2000WARE Hi,
I want to modify default SCI bootloader configuration pin (GPIO 28, GPIO29).
I want to use GPIO84 and GPIO85 for serial flash programming.
Please help me for bootloader source code…
Part Number: TMS320F28388D Hello,
I need to know the functionality of ERRORSTS ( Error status LED), why because i used the ERRORSTS led pin in my custom board
whenever I powered up the board it is getting ON and even after flashing the code into the target…
Part Number: TMS320F28388D Other Parts Discussed in Thread: SYSCONFIG Hi,
I can't find in Sysconfig how to configure the ADCs to use an external voltage reference.
The datasheet of the part mentions the possibility of using different external voltage…
Part Number: TMS320F28388D Hi,
Qshn is based on GPIO.
Suppose I have configured GPIO40 for Core1. Core1 can write into GPIO40. GPIO40 is configured for Core1. Can GPIO40 can be read by core2 also..?
Thanks,
Yamini
Part Number: TMS320F28388D Hello,
I'm using lwip to implement udp communication in CM core of TMS320f28388d.
and sometimes returns memory allocation error.
the code below is from f2838xif.c file
/*
* Get the head of the packet descriptor…
Part Number: TMS320F28388D Just want to provide some feedback.
I understand that TI is leaning into programming and configuration through driverlib, but IMO, the code style is inconsistent and often hard to read.
Here are a few examples found in ethernet…
Part Number: TMS320F28388D Hello,
I need to develop a software on 28388D with RTOS (must). I haven't used RTOS before.
I'll need to use PWM, GPIO, ADC, DMA, SPI, Ethernet MII (TCP/IP and UDP together), RS-422.
Data transfer with JSON, maybe with…
Part Number: TMS320F28388D Other Parts Discussed in Thread: TIDM-02011 I have Controller (TMS320F28388D). I Plan to live firmware update without device reset on F2838x( TMS320F28388D ) MCUs via SPI. For this, please provide a reference document or application…
Part Number: TMS320F28388D Hi,
Trying to move from basic IPC to message queue IPC.
I have a timer interrupt triggering an interrupt in core 1 to send a message using flag 1, which triggers an IPC interrupt on core 2 upon reception.
CPU1 sends a message…