Hi Gerold,
1. Is the load applied to the TPS40303 or the power module that supplies the VDD?
Benjamin: the load is applied to TPS40303. and TPS40303 VDD is powered by other power module which also has the OCP feature.
2. When you mention PGOOD…
Part Number: TPS40303 Hello,
I need to generate a 0.9V from a 12V input (17A max) and the design is highly constraint in efficiency.
I did look at the recommended TI parts for Altera/Intel but I need an efficiency above 90%. Which I achieved with…
Part Number: TPS40303 We read datasheet of TPS40303, in Functional Block Diagram, we know after power up, IC will enter Calibration, LDRV will disable.But we have question as:
When IC quit out from "Calibration" mode, OC function will also enable, what…
Part Number: TPS40303 What should happen to the TPS40303 when pin 2 is above the absolute maximum of 7V.
We are seeing low impedance between VDD (pin 1) and EN/SS (pin 2) due to surface corrosion caused by water. In many instances with 14VDC on VDD…
Just an update in case anyone else suffers the issue.
On initial power up the Boot PIn was seeing >37 volts for several dozen cycles.
Under running conditions it was ~27V
To lower this the High side fet gate drive was moved to 22R, Boot Resistor…
Other Parts Discussed in Thread: TPS40303 , TPS56921 Hello,
We would like to use the TPS40303 with Vin tied to a 3.3V rail, can we power Vdd with a dedicated 5.0V supply (e.g. REG711)?
My intent is to increase the BP voltage from approx. 3.3V to 5…
